Method of forming a semiconductor device having CMOS structures on a semiconductor substrate

Claim 1

A method of forming a semiconductor device on a semiconductor substrate, comprising the steps of: forming a silicon nitride layer on a surface of a semiconductor substrate; patterning the silicon nitride layer to have an opening over a first well region of the substrate and to have a nitride segment over a second well region of the substrate; implanting a first dopant of a first polarity into the substrate through the opening in the silicon nitride layer into the first well region, the nitride segment effectively shielding implantation of the first dopant into the second well region; growing a thick first silicon dioxide layer in the opening in the silicon nitride layer over the first well region, the nitride segment inhibiting growth of silicon dioxide over the second well region; removing the silicon nitride layer; implanting a second dopant of a second polarity opposite to the first polarity into the substrate, the first silicon dioxide layer effectively shielding implantation of the second dopant into the first well region; removing the first silicon dioxide layer; forming gate elements over channel regions in each of the first and second well regions respectively; forming source and drain regions in the substrate in each of the first and second well regions on opposite sides of the gate elements respectively; forming a second silicon dioxide layer which exhibits substantial thickening in an area on the surface of the substrate between the first and second well regions and in areas at the peripheries of the first and second well regions, and which is relatively thinner in remaining areas on the surface of the substrate, a top surface of the second silicon dioxide layer exhibiting an irregular topology; forming a third silicon dioxide layer over the second silicon dioxide layer, a top surface of the third silicon dioxide layer exhibiting an irregular topology; forming a fourth silicon dioxide layer over the third silicon dioxide layer; forming first vias through the fourth silicon dioxide layer, through the third silicon dioxide layer, and through the second silicon dioxide layer; forming metal plugs in the first vias to contact at least portions of the source/drain regions; forming a fifth silicon dioxide layer over the fourth silicon dioxide layer and over the metal plugs, a top surface of the fifth silicon dioxide layer exhibiting troughs and irregularities; applying a sixth silicon dioxide layer over the fifth silicon dioxide layer to smooth the troughs and irregularities in the top surface of the fifth silicon dioxide layer; forming a seventh silicon dioxide layer over the sixth silicon dioxide layer and portions of the fifth silicon dioxide layer which may be exposed through the sixth silicon dioxide layer; forming second vias through the seventh silicon dioxide layer, through the fifth layer of silicon dioxide, and through any via-aligned portions of the sixth silicon dioxide layer; applying a barrier metal layer over the seventh silicon dioxide layer, the barrier metal layer filling the second vias; applying a metal filler over the barrier metal layer; applying a metal cap over the metal filler; and applying one or more passivation layers over the metal cap and over the seventh silicon dioxide layer.

Claim 2

A method of forming a semiconductor device on a semiconductor substrate, comprising the steps of: forming a silicon nitride layer on a surface of a semiconductor substrate; patterning the silicon nitride layer to have an opening over a first well region of the substrate and to have a nitride segment over a second well region of the substrate; implanting a first dopant of a first polarity into the substrate through the opening in the silicon nitride layer into the first well region, the nitride segment effectively shielding implantation of the first dopant into the second well region; growing a thick first silicon dioxide layer in the opening in the silicon nitride layer over the first well region, the nitride segment inhibiting growth of silicon dioxide over the second well region; removing the silicon nitride layer; implanting a second dopant of a second polarity opposite to the first polarity into the substrate, the first silicon dioxide layer effectively shielding implantation of the second dopant into the first well region; removing the first silicon dioxide layer; forming gate elements over channel regions in each of the first and second well regions respectively; forming source and drain regions in the substrate in each of the first and second well regions on opposite sides of the gate elements respectively; forming a second silicon dioxide layer which exhibits substantial thickening in an area on the surface of the substrate between the first and second well regions and in areas at the peripheries of the first and second well regions, and which is relatively thinner in remaining areas on the surface of the substrate, a top surface of the second silicon dioxide layer exhibiting an irregular topology; forming a third silicon dioxide layer over the second silicon dioxide layer, a top surface of the third silicon dioxide layer exhibiting an irregular topology; forming a fourth silicon dioxide layer over the third silicon dioxide layer; forming first vias through the fourth silicon dioxide layer, through the third silicon dioxide layer, and through the second silicon dioxide layer; forming metal plugs in the first vias to contact at least portions of the source/drain regions; forming a fifth silicon dioxide layer over the fourth silicon dioxide layer and over the metal plugs, a top surface of the fifth silicon dioxide layer exhibiting troughs and irregularities; applying a sixth silicon dioxide layer over the fifth silicon dioxide layer to smooth the troughs and irregularities in the top surface of the fifth silicon dioxide layer; forming a seventh silicon dioxide layer over the sixth silicon dioxide layer and portions of the fifth silicon dioxide layer which may be exposed through the sixth silicon dioxide layer; forming second vias through the seventh silicon dioxide layer, through the fifth layer of silicon dioxide, and through any via-aligned portions of the sixth silicon dioxide layer; applying a barrier metal layer over the seventh silicon dioxide layer, the barrier metal layer filling the second vias; applying a metal filler over the barrier metal layer; applying a metal cap over the metal filler; and applying one or more passivation layers over the metal cap and over the seventh silicon dioxide layer.