Method of manufacturing a complementary MIS transistor

Claim 1

A method of manufacturing a CMOS transistor, comprising the steps of: (a) preparing a semiconductor substrate having a first region and a second region, said first region having a first conductivity type, said second region having a second conductivity type; (b) forming an insulating film covering surfaces of said first and said second regions; (c) forming a first gate electrode and a second gate electrode on said insulating film over said first and said second regions respectively; (d) implanting a first conductivity type impurity into said first and said second regions to form first diffusion regions, wherein said first and said second gate electrodes are used as a mask, an impurity concentration of said first diffusion region in said first region being higher than an impurity concentration of said first region other than said first diffusion region, said first diffusion region in said second region having said first conductivity type; (e) implanting a second conductivity type impurity into at least one of said first diffusion regions in said first region to form an offset region, said offset region having said second conductivity type, said one of said first diffusion regions being a double offset regions, at least a portion of said double offset region overlapping with said offset region (f) implanting a second conductivity type impurity into said first region to form a first source region and a first drain region, wherein said first source region and said first drain region have said second conductivity type, an impurity concentration of said offset region being lower than an impurity concentration of said first drain region, and said first drain region connected to said offset region, said offset region being disposed between said first gate electrode and said first drain region; and (g) implanting a first conductivity type impurity into said second region to form a second source region and a second drain region, an impurity concentration of said second source region and said second drain region being higher than an impurity concentration of said first diffusion regions, said second source region and said second drain region having said first conductivity type, said first diffusion region in said second region being disposed between said second gate electrode and said second drain region.

Claim 2

A method of manufacturing a CMOS transistor, comprising the steps of: (a) preparing a semiconductor substrate having a first region and a second region, said first region having a first conductivity type, said second region having a second conductivity type; (b) forming an insulating film covering surfaces of said first and said second regions; (c) forming a first gate electrode and a second gate electrode on said insulating film over said first and said second regions respectively; (d) implanting a first conductivity type impurity into said first and said second regions to form first diffusion regions, wherein said first and said second gate electrodes are used as a mask, an impurity concentration of said first diffusion region in said first region being higher than an impurity concentration of said first region other than said first diffusion region, said first diffusion region in said second region having said first conductivity type; (e) implanting a second conductivity type impurity into at least one of said first diffusion regions in said first region to form an offset region, said offset region having said second conductivity type, said one of said first diffusion regions being a double offset regions, at least a portion of said double offset region overlapping with said offset region (f) implanting a second conductivity type impurity into said first region to form a first source region and a first drain region, wherein said first source region and said first drain region have said second conductivity type, an impurity concentration of said offset region being lower than an impurity concentration of said first drain region, and said first drain region connected to said offset region, said offset region being disposed between said first gate electrode and said first drain region; and (g) implanting a first conductivity type impurity into said second region to form a second source region and a second drain region, an impurity concentration of said second source region and said second drain region being higher than an impurity concentration of said first diffusion regions, said second source region and said second drain region having said first conductivity type, said first diffusion region in said second region being disposed between said second gate electrode and said second drain region.