US4924277A
Expired / Lapsed
US
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MIS transistor device
Assignee: Denso Corp
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Filing: 1989-04-20
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Granted: 1990-05-08
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Expires: 2009-04-20
Abstract
Abstract In a MIS transistor device, a gate electrode is formed on a first conductivity-type well region formed in a semiconductor substrate. By implanting impurities with the gate electrode and an element-isolating region made up of a field insulating film as a mask, an N-type diffusion layer having a higher impurity concentration than the first conductivity-type well region is formed on the sides of the gate electrode. A second conductivity-type diffusion layer of a first impurity concentration higher than the N-type diffusion layer is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on one side of the gate electrode. A second conductivity-type diffusion layer of a second high concentration is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on the other side of the gate electrode.
Inventors
- 👤 Hiroyuki Yamane
- 👤 Yasushi Higuchi
- 👤 Tetsuo Fujii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:44
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10D30/00; H10D30/60; H10D30/601; H10D30/605; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D62/351; H10D62/357; H10D62/364; H10D62/371; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
373 words
A CMOS transistor device comprising: a semiconductor substrate; an N - type and a P - type well region formed in said semiconductor substrate; an insulating film formed on said N - type and said P - type well regions; a first and a second gate electrode formed on said insulating film respectively over said N - type and said P - type well regions; a first pair of N type diffusion layers formed in said N - type well region and separated by a portion underlying said first gate electrode, said first pair of N type diffusion layers having an impurity concentration of 3 to 30 times higher than an impurity concentration of said N - type well region; a second pair of N type diffusion layers formed in said P - type well region and separated by a portion underlying said second gate electrode, said second pair of N type diffusion layers having an impurity concentration of 3 to 30 times higher than an impurity concentration of said P - type well region; a first and a second P + type diffusion layer formed respectively in said first pair of N type diffusion layers formed in said N - type well region, and having widths respectively narrower than widths of said first pair of N type diffusion layers, said first and said second P + type diffusion layers having an impurity concentration higher than the impurity concentration of said first pair of N type diffusion layers; a first and a second N+ type diffusion layer formed respectively in said second pair of N type diffusion layers formed in said P - type well region, and having widths respectively narrower than widths of said second pair of N type diffusion layers, said first and said second N + type diffusion layers having an impurity concentration higher than the impurity concentration of said second pair of N type diffusion layers; a first and a second drain electrode respectively electrically connected to said first P + type diffusion layer and said first N + type diffusion layer; and a first and a second source electrode respectively electrically connected to said second P + -type diffusion layer and said second N + -type diffusion layer.
Claim 2
Dependent Claim
373 words
A CMOS transistor device comprising: a semiconductor substrate; an N - type and a P - type well region formed in said semiconductor substrate; an insulating film formed on said N - type and said P - type well regions; a first and a second gate electrode formed on said insulating film respectively over said N - type and said P - type well regions; a first pair of N type diffusion layers formed in said N - type well region and separated by a portion underlying said first gate electrode, said first pair of N type diffusion layers having an impurity concentration of 3 to 30 times higher than an impurity concentration of said N - type well region; a second pair of N type diffusion layers formed in said P - type well region and separated by a portion underlying said second gate electrode, said second pair of N type diffusion layers having an impurity concentration of 3 to 30 times higher than an impurity concentration of said P - type well region; a first and a second P + type diffusion layer formed respectively in said first pair of N type diffusion layers formed in said N - type well region, and having widths respectively narrower than widths of said first pair of N type diffusion layers, said first and said second P + type diffusion layers having an impurity concentration higher than the impurity concentration of said first pair of N type diffusion layers; a first and a second N+ type diffusion layer formed respectively in said second pair of N type diffusion layers formed in said P - type well region, and having widths respectively narrower than widths of said second pair of N type diffusion layers, said first and said second N + type diffusion layers having an impurity concentration higher than the impurity concentration of said second pair of N type diffusion layers; a first and a second drain electrode respectively electrically connected to said first P + type diffusion layer and said first N + type diffusion layer; and a first and a second source electrode respectively electrically connected to said second P + -type diffusion layer and said second N + -type diffusion layer.
Claim 3
Dependent Claim
72 words
A CMOS transistor device according to claim 1, wherein said first and said second P + type diffusion layer respectively extend in regions of said first pair of N type diffusion layers which are located under said first gate electrode, and said first and said second N + type diffusion layers respectively extend in regions of said second pair of N type diffusion layers which are located under said second gate electrode.
Claim 4
Dependent Claim
372 words
A CMOS transistor device comprising: a semiconductor substrate; an N - type and a P - type well region formed in said semiconductor substrate; an insulating film formed on said N - type and said P - type well region; a first and a second gate electrode formed on said insulating film respectively over said N - type and said P - type well region; a first pair of N type diffusion layers formed in said N - type well region and separated by a portion underlying said first gate electrode, said first pair of N type diffusion layers having an impurity concentration 15 to 20 times higher than an impurity concentration of said N - type well region; a second pair of N type diffusion layers formed in said P - type well region and separated by a portion underlying said second gate electrode, said second pair of N type diffusion layers having an impurity concentration 15 to 20 times higher than an impurity concentration of said P - type well region; a first and a second P + type diffusion layer formed respectively in said first pair of N type diffusion layers formed in said N - type well region, and having widths respectively narrower than widths of said first pair of N type diffusion layers, said first and said second P + type diffusion layer having an impurity concentration higher than the impurity concentration of said first pair of N type diffusion layers; a first and a second N + type diffusion layer formed respectively in said second pair of N type diffusion layers formed in said P - type well region, and having widths respectively narrower than widths of said second pair of N type diffusion layers, said first and said second N + type diffusion layer having an impurity concentration higher than the impurity concentration of said second pair of N type diffusion layers; a first and a second drain electrode respectively electrically connected to said first P + type diffusion layer and said first N + type diffusion layer; and a first and a second source electrode respectively electrically connected to said second P + type diffusion layer and said second N + -type diffusion layer.
Claim 5
Dependent Claim
372 words
A CMOS transistor device comprising: a semiconductor substrate; an N - type and a P - type well region formed in said semiconductor substrate; an insulating film formed on said N - type and said P - type well region; a first and a second gate electrode formed on said insulating film respectively over said N - type and said P - type well region; a first pair of N type diffusion layers formed in said N - type well region and separated by a portion underlying said first gate electrode, said first pair of N type diffusion layers having an impurity concentration 15 to 20 times higher than an impurity concentration of said N - type well region; a second pair of N type diffusion layers formed in said P - type well region and separated by a portion underlying said second gate electrode, said second pair of N type diffusion layers having an impurity concentration 15 to 20 times higher than an impurity concentration of said P - type well region; a first and a second P + type diffusion layer formed respectively in said first pair of N type diffusion layers formed in said N - type well region, and having widths respectively narrower than widths of said first pair of N type diffusion layers, said first and said second P + type diffusion layer having an impurity concentration higher than the impurity concentration of said first pair of N type diffusion layers; a first and a second N + type diffusion layer formed respectively in said second pair of N type diffusion layers formed in said P - type well region, and having widths respectively narrower than widths of said second pair of N type diffusion layers, said first and said second N + type diffusion layer having an impurity concentration higher than the impurity concentration of said second pair of N type diffusion layers; a first and a second drain electrode respectively electrically connected to said first P + type diffusion layer and said first N + type diffusion layer; and a first and a second source electrode respectively electrically connected to said second P + type diffusion layer and said second N + -type diffusion layer.
Claim 6
Dependent Claim
72 words
A CMOS transistor device according to claim 3, wherein said first and said second P + type diffusion layer respectively extend in regions of said first pair of N type diffusion layers which are located under said first gate electrode, and said first and said second N + type diffusion layers respectively extend in regions of said second pair of N type diffusion layers which are locate under said second gate electrode.
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