Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps

Claim 1

A field effect transistor architecture having source and drain regions of a first conductivity type disposed in a first semiconductor body portion of a second conductivity type, opposite to said first conductivity type, a gate electrode insulated from and overlying a surface of said first semiconductor body portion between said source and drain regions, a first field augmentation, channel stop region of said first conductivity type and having an impurity concentration increased relative to that of adjacent semiconductor material, formed beneath a field insulator layer overlying a second semiconductor body portion of said first conductivity type, and wherein said first field augmentation channel stop region has an impurity concentration profile the same as that of a lateral drift, drain extension region of said first conductivity type contiguous with said drain region of said first conductivity type, and further including a second field threshold augmentation region of said second conductivity type disposed in said first semiconductor body portion, so as to be spaced apart from said drain region of said first conductivity type of a high voltage MOS device, formed in said first semiconductor body portion, thereby avoiding a reduction in the drain-to-first body portion junction breakdown, and wherein said lateral drift region is formed as a dual conductivity type region having a first relatively deep impurity concentration region of said first conductivity type and a relatively shallow impurity concentration region of said second conductivity type, and wherein said first, relatively deep impurity concentration region has an impurity concentration profile the same as that of said first field augmentation channel stop region formed in said second semiconductor body portion, wherein said relatively shallow impurity concentration region of said second conductivity type has an impurity concentration profile corresponding to that of said second field augmentation region formed in said first semiconductor body portion.