High voltage MOS type semiconductor device

Abstract

Abstract PURPOSE:To optimize ion implantation in dose, to make a resistive layer long within a specified range, and to obtain a required CMOS of high breakdown strength by a method wherein an ion implanted resistive layer is formed in the same process that a channel stopper is formed. CONSTITUTION:A P-well 3 is formed on an N-type substrate 1, and a B ion implanted layer is formed between a channel stopper 6 of an N-channel FET and a gap 7 for a P-channel FET using an SiO2 4 and a resist 5 as masks, Then, P ions are implanted into a channel stopper 10 and a gap 11 for an N-channel FET using an SiO2 8 and a resist 9 as masks. Thereafter, the formation of a CMOSIC is completed through a usual method. The ion implanted layers formed on the gaps 7 and 11 between a channel and a drain under a gate are made to function as conductive layers when a drain voltage is low, and a voltage drop inside the implanted layers becomes large as a depletion layer spreads from the channel and the substrate when a drain voltage is high, and a drain voltage is absorbed by the implanted layers, so that a MOS type semiconductor device of this design can be improved in breakdown strength.

Inventors

• 👤 Tatsuji Asakawa
• 👤 浅川　辰司

Bibliographic Details