Lightly doped drain MOSFET with reduced on-resistance

Claim 2

MOSFET apparatus having reduced on-resistance and improved current characteristics, the apparatus comprising: a substrate region of first electrical conductivity type that has a top surface; source and drain regions, each more heavily doped than said substrate region, of second electrical conductivity type, spaced apart from each other and each forming a part of said top surface of said substrate region; a body region of second conductivity type material doped at a level intermediate that of said substrate region and said source region, surrounding said source region and forming a part of said top surface of said substrate region, so that said source region becomes an island in said body region; an oxide region having a top surface, being adjacent to said top surface of said substrate region, and including a semiconductor oxide material, overlying at least a portion of said source and drain regions and overlying substantially all of said substrate region that lies between said source and drain regions; a drift region positioned between said source and drain regions and forming a part of said top surface of said substrate region, spaced apart from at least one of said source region and said drain region and defining a gap therebetween, and forming a part of said top surface of said substrate region, said drift region being of second conductivity type; a gate overlying at least a portion of said gap and being positioned within the interior of said oxide region and overlying a portion of said substrate region that lies between said source and drain regions; means electrically connected to said gate for impressing a voltage on said gate; a second oxide region of high quality oxide, positioned between said gate and a portion of said top surface of said substrate region; a first electrical contact contiguous to said source region, a second electrical contact contiguous to said drain region, and a third electrical contact contiguous to said gate; a drift electrode of electrically conducting material positioned adjacent to said top surface of said oxide region, overlying at least a portion of said drift region and at most only a portion of said gate and having a voltage impressed on said drift electrode, to enhance the conductivity of said drift region when the MOSFET is on and to suppress the conductivity when the MOSFET is in the off-state; and means electrically connected to said drift electrode for impressing a first voltage on the drift electrode when the MOSFET is on and to impress a second voltage that differs from the first voltage when the MOSFET is not on, the first voltage being more positive than the voltage impressed on said gate.

Claim 3

Apparatus according to claim 1, wherein said drift electrode is spaced apart from said second electrical contact and from said third electrical contact by a distance of at least about two μm.

Claim 4

Apparatus according to claim 1, further including a drain plate that is electrically conducting, is electrically connected to said drain region, is positioned so that said drain plate overlies all or a portion of said drain region, and extends toward said source region.

Claim 5

Apparatus according to claim 1, further including means for maintaining said drift electrode at substantially ground potential.

Claim 6

Apparatus according to claim 1, further including means for maintaining said drift electrode at least at about a voltage of said gate.

Claim 7

Apparatus according to claim 1, further comprising: a source extension region contiguous to said source region, positioned under and adjacent to said oxide region and extending toward but being spaced apart from said drain region, said source extension region being contiguous to said source region and being of second conductivity type; a drain extension region contiguous to said drain region, positioned under and adjacent to said oxide region and extending toward but being spaced apart from said source region and said source extension region, said drain extension region being contiguous to said drain region and of second conductivity type; and where said gate is positioned so that it overlies substantially all of said substrate region that lies between said source extension region and the drain extension region.

Claim 8

The apparatus of claim 6, further comprising: a body contact region of first conductivity type, positioned contiguous to said source region, to said first electrical contact and to said substrate region.

Claim 9

Apparatus according to claim 6, further comprising: a spacer oxide region, including a low temperature thermal oxide of polysilicon, surrounding said gate and positioned within said interior of said oxide region, where said source region and said drain region are self-aligned using the spacer oxide region.

Claim 10

Apparatus according to claim 1, further comprising: a first source extension region of said source region, positioned under and adjacent to said oxide region and extending toward but being spaced apart from said drain region, with the source extension region being contiguous to said source region and being of second electrical conductivity type; a second source extension region of said source region, positioned under and adjacent to said oxide region contiguous to said source region and extending away from said drain region and being of second electrical conductivity type; a first drain extension region of said drain region, positioned under and adjacent to said oxide region and extending toward but being spaced apart from said source region and said source extension region, with said drain extension region being contiguous to said drain region and being of second electrical conductivity type; a second drain extension region, of said drain region, positioned under and adjacent to said oxide region and contiguous to said drain region and extending away from said source region and being of second electrical conductivity type; and wherein said gate overlies substantially all of said drift region that lies between said first source extension region and said first drain extension region.

Claim 11

Apparatus according to claim 1, further comprising: a buffer electrically connected at its output terminal to said gate and electrically connected at its input terminal to an input terminal for said MOSFET; an electrical connection of said source region contact to ground; a charge pump having an input terminal that is electrically connected to said input terminal of said buffer and having an output terminal that is electrically connected to said drift electrode; and an output terminal for said MOSFET that is electrically connected to said drain region.

Claim 12

Apparatus for shifting the voltage level of a p-channel MOSFET and an n-channel MOSFET relative to a reference voltage level, with each of these MOSFETs being constructed according to the apparatus of claim 1, the apparatus further comprising: a high voltage supply of voltage above ground potential electrically connected to said source region on said p-channel MOSFET; a first resistor of first resistance value having a first end thereof electrically connected to said high voltage supply; a second resistor of second resistance value having a first end thereof connected to a second end of said first resistor and to said gate region of said p-channel MOSFET, with a second end of said second resistor being connected to said drift electrode of each of said p-channel MOSFET and said n-channel MOSFET; a level shift MOSFET having a source, a gate and a drain, with its source electrically connected to a second end of said second resistor, its source electrically connected to ground and its gate electrically connected to an input terminal that receives an input signal; a buffer, with its input terminal electrically connected to said level shift MOSFET gate and its output terminal electrically connected to said gate region of said n-channel MOSFET; and an electrical connection of said source region of said n-channel MOSFET to ground.

Claim 13

Apparatus for shifting the voltage level of a p-channel MOSFET and an n-channel MOSFET relative to a reference voltage level, with each of these MOSFETs being constructed according to the apparatus of claim 1, the apparatus further comprising: a high voltage supply of voltage above ground potential electrically connected to said source region on said p-channel MOSFET; a first resistor of first resistance value having a first end thereof electrically connected to said high voltage supply; a second resistor of second resistance value having a first end thereof connected to a second end of said first resistor and to said gate region of said p-channel MOSFET; a level shift MOSFET having a source, a gate and a drain, with its drain electrically connected to a second end of said second resistor, its source electrically connected to ground and its gate electrically connected to an input terminal that receives an input signal; an electrical connection of said second end of said second resistor to said drift electrode of each of said p-channel MOSFET and said n-channel MOSFET and to said gate of said n-channel MOSFET; an electrical connection of said source region of said n-channel MOSFET to ground; and an electrical connection of said drain region of said p-channel MOSFET and said drain region of said n-channel MOSFET to an output terminal.

Claim 14

Apparatus for shifting the voltage level of a p-channel MOSFET and an n-channel MOSFET relative to a reference voltage level, with each of these MOSFETs being constructed according to the apparatus of claim 1, the apparatus further comprising: a high voltage supply of voltage above ground potential electrically connected to said source region of said p-channel MOSFET; first, second, third and fourth level shift MOSFETs each having a source, a gate and a drain, with said first and second of these MOSFETs being p-channel and said third and fourth of these MOSFETs being n-channel, with said source of each of these first and second MOSFETs being electrically connected to said high voltage supply and said sources of each of these third and fourth MOSFETs being electrically connected to ground; an electrical connection of said gate of said first level shift MOSFET, said drain of said second level shift MOSFET and said drain of said fourth level shift MOSFET to said drift electrode of each of said p-channel MOSFET and said n-channel MOSFET and to said gate of said p-channel MOSFET; an electrical connection of said gate of said second level shift MOSFET to said drain of said third level shift MOSFET and to said drain of said first level shift MOSFET; a buffer that is electrically connected at its input terminal to said gate of said third level shift MOSFET and to said reference voltage level and that is electrically connected at its output terminal to said gate of said fourth level shift MOSFET; an electrical connection between said gate of said p-channel MOSFET to said drift electrode of said p-channel MOSFET; an electrical connection between said source region of said p-channel MOSFET to said high voltage supply; and an electrical connection between said drain region of said p-channel MOSFET and said drain region of said n-channel MOSFET to an output terminal; and an electrical connection between said source region of said n-channel MOSFET to ground.

Claim 15

Apparatus for shifting the voltage level of a p-channel MOSFET and of an n-channel MOSFET relative to a reference voltage level, with each of these MOSFETs being constructed according to the apparatus of claim 1, the apparatus further comprising: a high voltage supply of voltage above ground potential electrically connected to said source region on said p-channel MOSFET; first, second, third and fourth level shift MOSFETs, each having a source, a gate and a drain, with said first and second of these MOSFETs being p-channel and said third and fourth of these MOSFETs being n-channel, with said source of each of these first and second MOSFETs being electrically connected to said high voltage supply and said sources of each of these third and fourth MOSFETs being electrically connected to ground; an electrical connection of said gate of said first level shift MOSFET, said drain of said second level shift MOSFET and said drain of said fourth level shift MOSFET to said drift electrode of each of said p-channel MOSFET and said n-channel MOSFET and to said gate region of each of said p-channel MOSFET and said n-channel MOSFET; an electrical connection of said gate of said second level shift MOSFET to said drain of said third level shift MOSFET and to said drain of said first level shift MOSFET; a buffer that is electrically connected at its input terminal to said gate of said third level shift MOSFET and to said reference voltage level and that is electrically connected at its output terminal to said gate of said fourth level shift MOSFET; an electrical connection of said source region of said p-channel MOSFET to said high voltage supply; electrically connecting said drain region of said p-channel MOSFET and said drain region of said n-channel MOSFET to an output terminal; an electrical connection of said source region of said n-channel MOSFET to ground; and an electrical connection together of said drift electrodes of said p-channel MOSFET and said n-channel MOSFET.

Claim 16

Apparatus for reducing the on-state resistance during voltage transition and improving the current characteristics of a p-channel MOSFET or an n-channel MOSFET, the apparatus comprising: a substrate region of a first electrical conductivity type that has a top surface; source and drain regions each more heavily doped than said substrate region, of second electrical conductivity type, spaced apart from each other and each forming a part of said top surface of said substrate; a body region of second conductivity type material doped at a level intermediate that of said substrate region and said source region, surrounding said source region and forming a part of said top surface of said substrate so that said source region becomes an island in said body region; an oxide region having a top surface, being adjacent to said top surface of said substrate, and including a semiconductor oxide material that overlies at least a portion of said source and drain regions and that overlies substantially all of said substrate region that lies between said source and drain regions; a drift region positioned between said source and drain regions and forming a part of said top surface of said substrate, spaced apart from at least one of said source region and said drain region and defining a gap therebetween, said drift region being of second electrical conductivity type; a gate overlying at least a portion of said gap and being positioned within the interior of said oxide region and overlying a portion of said substrate region that lies between said source and drain regions; means electrically connected to said gate for impressing a voltage on said gate; a second oxide region of high quality oxide, positioned between said gate and a portion of said top surface of said substrate; a first electrical contact contiguous to said source region, a second electrical contact contiguous to said drain region, and a third electrical contact contiguous to said gate; a drift electrode of electrically conducting material overlying at least a portion of said drift region and having a predetermined voltage impressed on said drift electrode, equal to the drain potential to enhance the conductivity of said drift region when the MOSFET is on during a voltage transition; and means electrically connected to said drift electrode for impressing a second voltage on said drift electrode when the MOSFET is on and to impress a third voltage that differs from said first voltage when the MOSFET is not on, the second voltage being more positive than the voltage impressed on said gate.

Claim 17

Apparatus for reducing the on-state resistance during voltage transition and improving the current characteristics of a p-channel MOSFET or an n-channel MOSFET, the apparatus comprising: a substrate region of a first electrical conductivity type that has a top surface; source and drain regions each more heavily doped than said substrate region, of second electrical conductivity type, spaced apart from each other and each forming a part of said top surface of said substrate; a body region of second conductivity type material doped at a level intermediate that of said substrate region and said source region, surrounding said source region and forming a part of said top surface of said substrate so that said source region becomes an island in said body region; an oxide region having a top surface, being adjacent to said top surface of said substrate, and including a semiconductor oxide material that overlies at least a portion of said source and drain regions and that overlies substantially all of said substrate region that lies between said source and drain regions; a drift region positioned between said source and drain regions and forming a part of said top surface of said substrate, spaced apart from at least one of said source region and said drain region and defining a gap therebetween, said drift region being of second electrical conductivity type; a gate overlying at least a portion of said gap and being positioned within the interior of said oxide region and overlying a portion of said substrate region that lies between said source and drain regions; means electrically connected to said gate for impressing a voltage on said gate; a second oxide region of high quality oxide, positioned between said gate and a portion of said top surface of said substrate; a first electrical contact contiguous to said source region, a second electrical contact contiguous to said drain region, and a third electrical contact contiguous to said gate; a drift electrode of electrically conducting material overlying at least a portion of said drift region and having a predetermined voltage impressed on said drift electrode, equal to the drain potential to enhance the conductivity of said drift region when the MOSFET is on during a voltage transition; and means electrically connected to said drift electrode for impressing a second voltage on said drift electrode when the MOSFET is on and to impress a third voltage that differs from said first voltage when the MOSFET is not on, the second voltage being more positive than the voltage impressed on said gate.

Claim 18

Apparatus for reducing the on-state resistance and improving the current characteristics of a MOSFET, the apparatus comprising: a well of material of a first electrical conductivity type that has a top surface and a bottom surface; a drain region more strongly doped than said well, of a second electrical conductivity type that is substantially opposite to the first conductivity type, with said drain region forming a part of said top surface of said well; first and second source regions, each more heavily doped than said drain region, of a second conductivity type and forming a part of said top surface of said well, with said two source regions being spaced apart from one another and each source region being spaced apart from said drain region, with said drain region being positioned between said first source region and said second source region; a first oxide region having a top surface, being adjacent to and above said top surface of said well, and including a semiconductor oxide material that overlies at least a portion of said drain region and said first source region and that overlies substantially all of said well that lies between said drain and first source regions; a second oxide region having a top surface, being adjacent to said top surface of said well, and including a semiconductor oxide material that overlies at least a portion of said drain region and said second source region and that overlies substantially all of said well that lies between said drain and second source regions; a first drift region positioned between said drain and first source regions and forming a part of said top surface of said well, spaced apart from at least one of said drain region and said first source region and defining a first gap therebetween, said first drift region being of second conductivity type; a second drift region positioned between said drain and second source regions and defining a part of said top surface of said well, spaced apart from at least one of said drain region and said second source region and forming a second gap therebetween, said second drift region being of second conductivity type; a first gate overlying at least a portion of said first gap and being positioned within the interior of said first oxide region and overlying a portion of said well that lies between said drain and first source regions; a second gate overlying at least a portion of said second gap and being positioned within the interior of said second oxide region and overlying a portion of said well that lies between said drain and second source regions; means electrically connected to both said gates for impressing a voltage on both said gates; a third oxide region of high quality oxide, positioned between said first gate and a portion of said top surface of said well; a fourth oxide region of high quality oxide, positioned between the second gate and a portion of said top surface of said well; a first drift electrode of electrically conducting material positioned adjacent to said top surface of said first oxide region, overlying at least a portion of said first drift region and at most only a portion of said first gate and having a voltage impressed on said first drift electrode which enhances the conductivity of said first drift region when the device is on and to suppress the conductivity when the device is in the off-state; a second drift electrode of electrically conducting material positioned adjacent to said top surface of said second oxide region, overlying at least a portion of said second drift region and at most a portion of said second gate and having a voltage impressed on said second drift electrode which enhances the conductivity of said second drift region when the device is on and suppresses the conductivity when the apparatus is off, where said first and second drift electrodes may be electrically connected to each other; a buried layer, including material of first conductivity type, positioned adjacent to the bottom surface of said well and underlying substantially all of said first and second source regions, first and second drift regions and drain region; a first body contact region, including material of first conductivity type, forming a part of said top surface of said well and being positioned contiguous to said first source region and to said well so that said first source region lies between said first body contact region and said drain region; a second body contact region, including material of first conductivity type, forming a part of said top surface of said well and being positioned contiguous to said second source region so that said second source region lies between said second body contact region and said drain region; and a first electrical contact contiguous to said first source region and to said first body contact region, a second electrical contact contiguous to said second source region and to said second body contact region, a third electrical contact contiguous to said first gate, a fourth electrical contact contiguous to said second gate, and a fifth electrical contact contiguous to said drain region.

Claim 19

Apparatus for reducing the on-state resistance and improving the current characteristics of a MOSFET, the apparatus comprising: a well of material of a first electrical conductivity type that has a top surface and a bottom surface; a drain region more strongly doped than said well, of a second electrical conductivity type that is substantially opposite to the first conductivity type, with said drain region forming a part of said top surface of said well; first and second source regions, each more heavily doped than said drain region, of a second conductivity type and forming a part of said top surface of said well, with said two source regions being spaced apart from one another and each source region being spaced apart from said drain region, with said drain region being positioned between said first source region and said second source region; a first oxide region having a top surface, being adjacent to and above said top surface of said well, and including a semiconductor oxide material that overlies at least a portion of said drain region and said first source region and that overlies substantially all of said well that lies between said drain and first source regions; a second oxide region having a top surface, being adjacent to said top surface of said well, and including a semiconductor oxide material that overlies at least a portion of said drain region and said second source region and that overlies substantially all of said well that lies between said drain and second source regions; a first drift region positioned between said drain and first source regions and forming a part of said top surface of said well, spaced apart from at least one of said drain region and said first source region and defining a first gap therebetween, said first drift region being of second conductivity type; a second drift region positioned between said drain and second source regions and defining a part of said top surface of said well, spaced apart from at least one of said drain region and said second source region and forming a second gap therebetween, said second drift region being of second conductivity type; a first gate overlying at least a portion of said first gap and being positioned within the interior of said first oxide region and overlying a portion of said well that lies between said drain and first source regions; a second gate overlying at least a portion of said second gap and being positioned within the interior of said second oxide region and overlying a portion of said well that lies between said drain and second source regions; means electrically connected to both said gates for impressing a voltage on both said gates; a third oxide region of high quality oxide, positioned between said first gate and a portion of said top surface of said well; a fourth oxide region of high quality oxide, positioned between the second gate and a portion of said top surface of said well; a first drift electrode of electrically conducting material positioned adjacent to said top surface of said first oxide region, overlying at least a portion of said first drift region and at most only a portion of said first gate and having a voltage impressed on said first drift electrode which enhances the conductivity of said first drift region when the device is on and to suppress the conductivity when the device is in the off-state; a second drift electrode of electrically conducting material positioned adjacent to said top surface of said second oxide region, overlying at least a portion of said second drift region and at most a portion of said second gate and having a voltage impressed on said second drift electrode which enhances the conductivity of said second drift region when the device is on and suppresses the conductivity when the apparatus is off, where said first and second drift electrodes may be electrically connected to each other; a buried layer, including material of first conductivity type, positioned adjacent to the bottom surface of said well and underlying substantially all of said first and second source regions, first and second drift regions and drain region; a first body contact region, including material of first conductivity type, forming a part of said top surface of said well and being positioned contiguous to said first source region and to said well so that said first source region lies between said first body contact region and said drain region; a second body contact region, including material of first conductivity type, forming a part of said top surface of said well and being positioned contiguous to said second source region so that said second source region lies between said second body contact region and said drain region; and a first electrical contact contiguous to said first source region and to said first body contact region, a second electrical contact contiguous to said second source region and to said second body contact region, a third electrical contact contiguous to said first gate, a fourth electrical contact contiguous to said second gate, and a fifth electrical contact contiguous to said drain region.

Claim 20

Apparatus according to claim 16, wherein: said first and second drift regions are connected parts of a substantially annular shaped drift region that surrounds, in a lateral plane, said drain region; said first and second gaps are part of a substantially annular shaped gap; said first and second source regions are part of a substantially annular shaped source region; said first and second body contact regions are part of a substantially annular shaped isolation region; said first and second oxide regions are part of a substantially annular shaped oxide region; said first and second gates are part of a substantially annular shaped gate; and said first and second drift electrodes are part of a substantially annular shaped drift electrode.

Claim 21

Apparatus for reducing the on-state resistance of, and improving the current characteristics of, a MOSFET, apparatus comprising: a substrate region of first electrical conductivity type that has a top surface; source and drain regions of second conductivity type, more heavily doped than said substrate region, spaced apart from each other and each forming a part of said top surface of said substrate region; a drift region of second electrical conductivity type opposite to that of the first conductivity type, formed at said top surface of said substrate and of a predetermined thickness having an interface with said substrate region, and extending between said source region and said drain region; a buried layer of first conductivity type, doped at a level intermediate that of said substrate region and said source region, that is adjacent to a portion of the substrate region-drift region interface; a body region of first conductivity type in said substrate region top surface that surrounds said source region so that said source region becomes an island in said body region, with said body region being spaced apart laterally from said drain region and being spaced apart vertically from said buried layer; an oxide region having a top surface, being adjacent to the top surface of said drift region, and including a semiconductor oxide material, overlying at least a portion of said source and drain regions and overlying substantially all of said drift region that lies between said source and drain regions; a gate overlying at least a portion of said drift region and being positioned within the interior of said oxide region and overlying a portion of said drift region that lies between said source and drain regions; means electrically connected to said gate for impressing a voltage on said gate; a second oxide region of high quality oxide, positioned between said gate and a portion of said top surface of said substrate; and a drift electrode of electrically conducting material positioned adjacent to said top surface of said oxide region, overlying at least a portion of said drift region and at most only a portion of said gate and having a voltage impressed on said drift electrode, to enhance the conductivity of said drift region when the MOSFET is on and to suppress the conductivity when the MOSFET is in an off-state, the voltage impressed on said drift electrode being more positive than the voltage impressed on said gate when the MOSFET is on.

Claim 22

Apparatus for reducing the on-state resistance of, and improving the current characteristics of, a MOSFET, apparatus comprising: a substrate region of first electrical conductivity type that has a top surface; source and drain regions of second conductivity type, more heavily doped than said substrate region, spaced apart from each other and each forming a part of said top surface of said substrate region; a drift region of second electrical conductivity type opposite to that of the first conductivity type, formed at said top surface of said substrate and of a predetermined thickness having an interface with said substrate region, and extending between said source region and said drain region; a buried layer of first conductivity type, doped at a level intermediate that of said substrate region and said source region, that is adjacent to a portion of the substrate region-drift region interface; a body region of first conductivity type in said substrate region top surface that surrounds said source region so that said source region becomes an island in said body region, with said body region being spaced apart laterally from said drain region and being spaced apart vertically from said buried layer; an oxide region having a top surface, being adjacent to the top surface of said drift region, and including a semiconductor oxide material, overlying at least a portion of said source and drain regions and overlying substantially all of said drift region that lies between said source and drain regions; a gate overlying at least a portion of said drift region and being positioned within the interior of said oxide region and overlying a portion of said drift region that lies between said source and drain regions; means electrically connected to said gate for impressing a voltage on said gate; a second oxide region of high quality oxide, positioned between said gate and a portion of said top surface of said substrate; and a drift electrode of electrically conducting material positioned adjacent to said top surface of said oxide region, overlying at least a portion of said drift region and at most only a portion of said gate and having a voltage impressed on said drift electrode, to enhance the conductivity of said drift region when the MOSFET is on and to suppress the conductivity when the MOSFET is in an off-state, the voltage impressed on said drift electrode being more positive than the voltage impressed on said gate when the MOSFET is on.

Claim 23

A transistor having reduced on-resistance comprising: a substrate of first conductivity type and having a top surface; spaced-apart source and drain formed in said substrate and extending to said top surface, each of second conductivity type; an insulating layer formed on said top surface; a drift region formed in said substrate between said source and said drain, being of the second conductivity type; a conductive gate overlying said insulating layer and a portion of said substrate between said source and said drain; means for impressing a voltage on said conductive gate; a drift electrode overlying said insulating layer and at least a portion of said drift region for selectively altering the conductivity of said drain region; and means for impressing a switchable voltage on said drift electrode, the voltage being independent of a voltage of said drain and more positive than the voltage impressed on said conductive gate when the transistor is on.

Claim 24

A transistor having reduced on-resistance comprising: a substrate of first conductivity type and having a top surface; spaced-apart source and drain formed in said substrate and extending to said top surface, each of second conductivity type; an insulating layer formed on said top surface; a drift region formed in said substrate between said source and said drain, being of the second conductivity type; a conductive gate overlying said insulating layer and a portion of said substrate between said source and said drain; means for impressing a voltage on said conductive gate; a drift electrode overlying said insulating layer and at least a portion of said drift region for selectively altering the conductivity of said drain region; and means for impressing a switchable voltage on said drift electrode, the voltage being independent of a voltage of said drain and more positive than the voltage impressed on said conductive gate when the transistor is on.

Claim 25

The device of claim 19, wherein said drift region has an effective dose of dopant in a range of about 5×10 10 to 5×10 12 dopant atoms/cm 2 .

Claim 26

The device of claim 19, wherein said drift electrode overlies at most only a portion of said conductive gate.

Claim 27

The device of claim 19, further comprising a conductive plate overlying a portion of said insulating layer and a portion of said drain.