Semiconductor device of complementary integrated circuit

Claim 2

A semiconductor device of a complementary integrated circuit, comprising: an n-semiconductor substrate; a p-well formed with said n-semiconductor substrate; an n-channel FET (field effect transistor) formed on said p-well, said n-channel FET including an n-source connected to a first grounded line and an n-drain connected to an output line; a p-channel FET formed on said n-semiconductor substrate, said p-channel FET including a p-source connected to a first voltage source line and a p-drain connected to said output line; a contact p-region formed on said p-well for providing electrical connection between said p-well and a second grounded line; and a contact n-region formed on said n-semiconductor substrate for providing electrical connection between said n-semiconductor substrate and a second voltage source line.

Claim 3

A semiconductor device of a complementary integrated circuit, comprising: a p-semiconductor substrate; an n-well formed within said p-semiconductor substrate; an n-channel FET formed on said p-semiconductor substrate, said n-channel FET including an n-source connected to a first grounded line and an n-drain connected to an output line; a p-channel FET formed on said n-well, said p-channel FET including a p-source connected to a voltage source line and a p-drain connected to said output line; a contact p-region formed on said p-semiconductor substrate for providing electrical connection between said p-semiconductor substrate and a second grounded line; and a contact n-region formed on said n-well for providing electrical connection between said n-well and a second voltage source line.

Claim 4

A semiconductor device of a complementary integrated circuit, comprising: a p-semiconductor substrate; an n-well formed within said p-semiconductor substrate; an n-channel FET formed on said p-semiconductor substrate, said n-channel FET including an n-source connected to a first grounded line and an n-drain connected to an output line; a p-channel FET formed on said n-well, said p-channel FET including a p-source connected to a voltage source line and a p-drain connected to said output line; a contact p-region formed on said p-semiconductor substrate for providing electrical connection between said p-semiconductor substrate and a second grounded line; and a contact n-region formed on said n-well for providing electrical connection between said n-well and a second voltage source line.

Claim 5

A semiconductor device of a complementary integrated circuit, comprising: an semiconductor substrate; an n-well and p-well formed with said semiconductor substrate; an n-channel FET formed on said p-well, said n-channel FET including an n-source connected to a first grounded line and an n-drain connected to an output line; a p-channel FET formed on said n-well, said p-channel FET including a p-source connected to a first voltage source line and a p-drain connected to said output line; a contact p-region formed on said p-well for providing electrical connection between said p-well and a second grounded line; and a contact n-region formed on said n-well for providing electrical connection between said n-well and a second voltage source line.

Claim 6

A semiconductor device of a complementary integrated circuit, comprising: an semiconductor substrate; an n-well and p-well formed with said semiconductor substrate; an n-channel FET formed on said p-well, said n-channel FET including an n-source connected to a first grounded line and an n-drain connected to an output line; a p-channel FET formed on said n-well, said p-channel FET including a p-source connected to a first voltage source line and a p-drain connected to said output line; a contact p-region formed on said p-well for providing electrical connection between said p-well and a second grounded line; and a contact n-region formed on said n-well for providing electrical connection between said n-well and a second voltage source line.

Claim 7

In a complementary integrated circuit having complementary first and second field effect transistors, each transistor including source and drain regions of one conductivity type and a contact region of an opposite conductivity type, said first transistor formed in a substrate and said second transistor formed in a well in said substrate, the improvement comprising: a structural arrangement for reducing spread of noise surges from an output line connected to said drain regions of said first and second field effect transistors to said substrate or to said well, including separate voltage source lines connected to said source and contact regions of each of the complementary first and second field effect transistors.

Claim 8

In a complementary integrated circuit having complementary first and second field effect transistors, each transistor including source and drain regions of one conductivity type and a contact region of an opposite conductivity type, said first transistor formed in a substrate and said second transistor formed in a well in said substrate, the improvement comprising: a structural arrangement for reducing spread of noise surges from an output line connected to said drain regions of said first and second field effect transistors to said substrate or to said well, including separate voltage source lines connected to said source and contact regions of each of the complementary first and second field effect transistors.

Claim 9

In a complementary integrated circuit including a substrate of a first conductivity type, a first field effect transistor having a conductivity of a second conductivity type opposite to said first conductivity type, said first field effect transistor having a first channel between a first source and a first drain of said second conductivity type, said first field effect transistor further including a first contact region of said first conductivity type and a first voltage level connected to said first source and to said first contact region; a well of said second conductivity type within said substrate, a second field effect transistor having a second source and a second drain of said first conductivity type formed on said well, and a second contact region of said second conductivity type formed on said well, a second voltage level connected to said second source and to said second contact region, the improvement comprising: a structural arrangement for reducing spread of noise surges from an output line connected to said drains of said first and second field effect transistors to said substrate or to said well, including first and second voltage lines for providing said first voltage level to said first source and to said first contact region, respectively, and third and fourth voltage lines for providing said second voltage level to said second source and to said second contact region, respectively.

Claim 10

In a complementary integrated circuit including a substrate of a first conductivity type, a first field effect transistor having a conductivity of a second conductivity type opposite to said first conductivity type, said first field effect transistor having a first channel between a first source and a first drain of said second conductivity type, said first field effect transistor further including a first contact region of said first conductivity type and a first voltage level connected to said first source and to said first contact region; a well of said second conductivity type within said substrate, a second field effect transistor having a second source and a second drain of said first conductivity type formed on said well, and a second contact region of said second conductivity type formed on said well, a second voltage level connected to said second source and to said second contact region, the improvement comprising: a structural arrangement for reducing spread of noise surges from an output line connected to said drains of said first and second field effect transistors to said substrate or to said well, including first and second voltage lines for providing said first voltage level to said first source and to said first contact region, respectively, and third and fourth voltage lines for providing said second voltage level to said second source and to said second contact region, respectively.

Claim 11

An improved complementary integrated circuit as recited in claim 5 wherein said first conductivity type is an n conductivity type and said second conductivity type is a p conductivity type, said first field effect transistor having p-type source and drain and n-type contact region, said second field effect transistor being formed in a p-type well within an n-type substrate and including n-type source and drain and p-type contact region.

Claim 12

A semiconductor device as recited in claim 1, wherein said p-source is in an area substantially beneath a first source electrode connecting only said p-source to said first voltage source line and said n-source is in an area substantially beneath a second source electrode connecting only said n-source to said first grounded line.

Claim 13

A semiconductor device as recited in claim 7, wherein said contact n-region is in an area substantially beneath a first contact electrode connecting only said contact n-region to said second voltage source line and said contact p-region is in an area substantially beneath a second contact electrode connecting only said contact p-region to said second grounded line.

Claim 14

A semiconductor device as recited in claim 8, wherein said contact n-region is arranged substantially in a straight line orientation with respect to said p-source and said p-drain, and said contact p-region is arranged substantially in a straight line orientation with respect to said n-source and said n-drain.

Claim 15

A semiconductor device as recited in claim 2, wherein said p-source is in an area substantially beneath a first source electrode connecting only said p-source to said first voltage source line and said n-source is in an area substantially beneath a second source electrode connecting only said n-source to said first grounded line.

Claim 16

A semiconductor device as recited in claim 10, wherein said contact n-region is in an area substantially beneath a first contact electrode connecting only said contact n-region to said second voltage source line and said contact p-region is in an area substantially beneath a second contact electrode connecting only said contact p-region to said second grounded line.

Claim 17

A semiconductor device as recited in claim 11, wherein said contact n-region is arranged substantially in a straight line orientation with respect to said p-source and said p-drain, and said contact p-region is arranged substantially in a straight line orientation with respect to said n-source and said n-drain.

Claim 18

A semiconductor device as recited in claim 5, wherein said first source is in an area substantially beneath a first source electrode connecting only said first source to said first voltage line and said second source is in an area substantially beneath a second source electrode connecting only said second source to said third voltage line.

Claim 19

A semiconductor device as recited in claim 13, wherein said first contact region is in an area substantially beneath a first contact electrode connecting only said first contact region to said second voltage line and said second contact region is in an area substantially beneath a second contact electrode connecting only said second contact region to said fourth voltage line.

Claim 20

A semiconductor device as recited in claim 14, wherein said first contact region is arranged substantially in a straight line orientation with respect to said first source and said first drain, and said second contact region is arranged substantially in a straight line orientation with respect to said second source and said second drain.

Claim 21

An improved complementary integrated circuit as recited in claim 5, wherein said first field effect transistor includes a first gate defining said first channel and said second field effect transistor includes a second gate defining a second channel between said second source and said second drain, said first contact region of said first conductivity type in said first field effect transistor including a boundary portion parallel to said first gate and said second contact region of said second conductivity type in said second field effect transistor including a boundary portion parallel to said second gate.

Claim 22

In a complementary integrated circuit having complementary first and second field effect transistors, each transistor including source and drain regions of one conductivity type and a contact region of an opposite conductivity type, said first and second field effect transistor further including first and second gates, respectively, defining respective first and second channels between respective source and drain regions thereof, said first field effect transistor formed in a substrate and said second field effect transistor formed in a well in said substrate, the improvement comprising: a structural arrangement for reducing spread of noise surges from an output line connected to said drain regions of said first and second field effect transistors to said substrate or to said well, said structural arrangement including separate voltage source lines connected to said source and contact regions of each of the complementary transistors, wherein said contact regions in said first and second field effect transistors are respectively separated from said first and second channels defined by said first and second gates, thereby increasing a dimension of a boundary between the respective sources and channels of said first and second field effect transistors, whereby a current transfer capacity between the respective sources and channels of said transistors is increased.

Claim 23

In a complementary integrated circuit having complementary first and second field effect transistors, each transistor including source and drain regions of one conductivity type and a contact region of an opposite conductivity type, said first and second field effect transistor further including first and second gates, respectively, defining respective first and second channels between respective source and drain regions thereof, said first field effect transistor formed in a substrate and said second field effect transistor formed in a well in said substrate, the improvement comprising: a structural arrangement for reducing spread of noise surges from an output line connected to said drain regions of said first and second field effect transistors to said substrate or to said well, said structural arrangement including separate voltage source lines connected to said source and contact regions of each of the complementary transistors, wherein said contact regions in said first and second field effect transistors are respectively separated from said first and second channels defined by said first and second gates, thereby increasing a dimension of a boundary between the respective sources and channels of said first and second field effect transistors, whereby a current transfer capacity between the respective sources and channels of said transistors is increased.