US4053916A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Silicon on sapphire MOS transistor
Assignee: Westinghouse Electric Corp
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Filing: 1975-09-04
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Granted: 1977-10-11
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Expires: 1995-09-04
Abstract
Abstract An MOS transistor constructed using silicon on sapphire technology in which the channel region can be electrically connected either to the source or drain terminal is disclosed. The transistor is advantageous in that the shift of the threshold voltage of the transistor in the presence of radiation is substantially decreased. Connecting the channel region of the transistor to the source terminal also substantially reduces what is normally referred to as the "kink" effect in MOS transistors utilizing floating substrate channel regions. Reducing the sensitivity to radiation and the kink effect results in a transistor having improved electrical characteristics.
Inventors
- 👤 James R. Cricchi
- 👤 Michael D. Fitzpatrick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:11
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6708; H10D30/6711
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
114 words
A planar transistor comprising a. a semiconductive structure including: 1. a channel region of a first conductivity type interposed between drain and source regions of a second conductivity type, 2. at least one high conductivity region of said first conductivity type contiguous to said source and channel regions; b. an insulating layer overlying said channel region; c. an electrically conductive layer overlying said insulating layer to form the gate of said transistor; d. electrically conductive means electrically coupled to said drain region to form the drain terminal of said transistor; and e. electrically conductive means coupled to said source region and to said high conductivity region to form the source terminal of said transistor.
Claim 2
Dependent Claim
114 words
A planar transistor comprising a. a semiconductive structure including: 1. a channel region of a first conductivity type interposed between drain and source regions of a second conductivity type, 2. at least one high conductivity region of said first conductivity type contiguous to said source and channel regions; b. an insulating layer overlying said channel region; c. an electrically conductive layer overlying said insulating layer to form the gate of said transistor; d. electrically conductive means electrically coupled to said drain region to form the drain terminal of said transistor; and e. electrically conductive means coupled to said source region and to said high conductivity region to form the source terminal of said transistor.
Claim 3
Dependent Claim
143 words
A planar MOS transistor having gate, source and drain terminals comprising: a. a semiconductive structure including: 1. drain and source regions of a first conductivity type, 2. a channel region of second conductivity type interposed between said drain and source regions, 3. at least one electrically conductive region of said second conductivity type forming a low resistance path to said channel region; b. an electrically insulating layer overlying said channel region; c. first electrically conductive means overlying said insulating layer to form the gate terminal of said transistor; d. second electrically conductive means forming an electrically conductive path to said drain region to form said drain terminal; e. third electrically conductive means coupled through a low resistance path to said source region and to said at least one electrically conductive region of said second conductivity type to form the source of said transistor.
Claim 4
Dependent Claim
143 words
A planar MOS transistor having gate, source and drain terminals comprising: a. a semiconductive structure including: 1. drain and source regions of a first conductivity type, 2. a channel region of second conductivity type interposed between said drain and source regions, 3. at least one electrically conductive region of said second conductivity type forming a low resistance path to said channel region; b. an electrically insulating layer overlying said channel region; c. first electrically conductive means overlying said insulating layer to form the gate terminal of said transistor; d. second electrically conductive means forming an electrically conductive path to said drain region to form said drain terminal; e. third electrically conductive means coupled through a low resistance path to said source region and to said at least one electrically conductive region of said second conductivity type to form the source of said transistor.
Claim 5
Dependent Claim
159 words
A planar MOS transistor having a gate, source and drain terminals, comprising in combination; a. a semiconductive structure supported on an electrically insulating substrate, said semiconductive structure comprising; 1. drain and source regions of a first conductivity type, 2. a channel region of a second conductivity type interposed between said drain and source region, 3. at least one electrically conductivity region of said second conductivity type forming a low resistance path to said channel region; b. an electrically insulating layer overlying said channel region; c. first electrically conductive means overlying said insulating layer to form said gate terminal; d. second electrically conductive means coupled through a low resistance path to said drain region to form the drain terminal by said transistor; and e. third electrically conductive means coupled through a low resistance path to said source region and to said at least one electrically conductive region of said second conductivity type to form the source terminal of said transistor.
Claim 6
Dependent Claim
159 words
A planar MOS transistor having a gate, source and drain terminals, comprising in combination; a. a semiconductive structure supported on an electrically insulating substrate, said semiconductive structure comprising; 1. drain and source regions of a first conductivity type, 2. a channel region of a second conductivity type interposed between said drain and source region, 3. at least one electrically conductivity region of said second conductivity type forming a low resistance path to said channel region; b. an electrically insulating layer overlying said channel region; c. first electrically conductive means overlying said insulating layer to form said gate terminal; d. second electrically conductive means coupled through a low resistance path to said drain region to form the drain terminal by said transistor; and e. third electrically conductive means coupled through a low resistance path to said source region and to said at least one electrically conductive region of said second conductivity type to form the source terminal of said transistor.
Claim 7
Dependent Claim
182 words
A planar MOS transistor comprising a drain and source with a channel interposed therebetween: a. a semiconductive structure comprising: 1. drain of a first conductivity type, 2. a region including alternating portions of said first conductivity type and a second conductivity type with said portions of said first conductivity type forming the source of said transistor with said portions of said second conductivity type forming a low resistance path to a channel region of said second conductivity type interposed between said drain and source regions; b. an electrically insulating layer overlying said channel regon; c. a first electrically conductive layer overlying said insulating layer to form a gate terminal of said transistor; d. first electrically conductive means coupled through a low resistance path to said drain region to form the drain terminal of said transistor; e. second electrically conductive means coupled to said source to form the source terminal of said transistor; f. third electrically conductive means coupled to the portion of said region having said second conductivity type to provide a terminal coupled to said channel through a low resistance path.
Claim 8
Dependent Claim
182 words
A planar MOS transistor comprising a drain and source with a channel interposed therebetween: a. a semiconductive structure comprising: 1. drain of a first conductivity type, 2. a region including alternating portions of said first conductivity type and a second conductivity type with said portions of said first conductivity type forming the source of said transistor with said portions of said second conductivity type forming a low resistance path to a channel region of said second conductivity type interposed between said drain and source regions; b. an electrically insulating layer overlying said channel regon; c. a first electrically conductive layer overlying said insulating layer to form a gate terminal of said transistor; d. first electrically conductive means coupled through a low resistance path to said drain region to form the drain terminal of said transistor; e. second electrically conductive means coupled to said source to form the source terminal of said transistor; f. third electrically conductive means coupled to the portion of said region having said second conductivity type to provide a terminal coupled to said channel through a low resistance path.
Claim 9
Dependent Claim
19 words
A transistor in accordance with claim 1 further including an insulating substrate on which said semiconductor structure is formed.
Claim 10
Dependent Claim
13 words
A transistor in accordance with claim 5 wherein said insulating substrate is sapphire.
Claim 11
Dependent Claim
14 words
A transistor in accordance with claim 1 wherein said first conductivity type is P.
Claim 12
Dependent Claim
14 words
A transistor in accordance with claim 1 wherein said first conductivity type is N.
Claim 13
Dependent Claim
19 words
A transistor in accordance with claim 3 further including a plurality of said regions of a second conductivity type.
Claim 14
Dependent Claim
39 words
A transistor in accordance with claim 9 wherein said plurality of regions of a second conductivity type are interdigitated with regions of said first conductivity type, said regions of said first conductivity type forming the source of said transistor.
References Cited (Backward Citations)
US3484662A
Cited
US3590342A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-10 | 1981-04-11 | 1981-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-10 | 1985-04-11 | 1985-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-10 | 1989-04-11 | 1989-10-11 | $7700.00 | Window Closed / Lapsed |