Method for manufacturing integrated dynamic RAM one-transistor storage cells

Claim 1

Method for manufacturing dynamic RAM one-transistor cells integrated in a semiconductor substrate, each cell consisting of one field-effect transistor and one storage capacitor, which comprises (a) insulating areas of the semiconductor substrate for the one-transistor cells by thick oxide structures to insulate the cells from each other and covering the areas for the cells between the thick oxide structures with first thin oxide layers, (b) forming an electrode for the storage capacitors by applying a first polycrystalline semiconductor layer over the entire surface of the thick oxide structures and the first thin oxide layers, and structuring by etching in the areas of the semiconductor substrate together with the first thin oxide layers, to leave remaining on the storage capacitor parts of the one-transistor cell areas of the semiconductor substrate a layer sequence of thin oxide as a capacitor dielectric and the polycrystalline layer as the capacitor electrode, (c) applying a second thin oxide layer over the entire surface to form a gate oxide for the transistors, (d) doping the transistor parts of the one-transistor cell areas of the semiconductor substrate by another ion implantation to adjust the cut-off voltage of the transistors, (e) forming the gate electrodes of the transistors, by applying a second polycrystalline semiconductor layer over the entire surface and structuring by etching to leave parts of the second polycrystalline semiconductor on the transistor parts of the one-transistor cell areas, the combination therewith of (f) adjusting the storage capacitors to a predetermined storage capacity after the thick oxide structures and the first thin oxide layers are formed, and using the thick oxide structures as a mask, subjecting the cell areas to an ion implantation for preparing a doped layer which with the semiconductor substrate forms a pn-junction in the storage capacitor parts in the semiconductor substrate, and (g) performing said another ion implantation for adjusting the cut-off voltage of the transfer transistors utilizing as a mask the parts of the first polycrystalline semiconductor layer which form the electrode of the storage capacitors.