US5473183A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device of a first conductivity type which has a first well of a second conductivity type formed therein and a second well of the first conductivity type formed in the first well and a pair of MOSFET formed in the first and second wells
Assignee: Sony Corp
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Filing: 1994-09-07
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Granted: 1995-12-05
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Expires: 2014-09-07
Abstract
Abstract The present invention is directed to a CMOS inverter in which an N-FET (Qn) formed of an N-type source region (2S), a drain region (2D) and a gate electrode (2G) and a P-FET (Qp) formed of a P-type source region (3S), a drain region (3D) and a gate electrode (3G) are formed on an N-type silicon substrate (1n). A first well region (4p) is formed under the N-FET (Qn) and P-FET (Qp). Further, an N-type well region (5n) is formed on the P-FET (Qp) within the first well region (4p). Thus, an influence exerted by a back-gate effect from the substrate can be prevented completely, whereby a phase displacement relative to a pulse response to a CMOS peripheral logic circuit and a malfunction can be avoided.
Inventors
- 👤 Kazuya Yonemoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:04
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S257/00; Y10S257/901
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
121 words
A semiconductor device having a semiconductor substrate supplied with a fluctuating voltage comprising: said semiconductor substrate of a first conductivity type; a first well of a second conductivity type formed in said semiconductor substrate; a second well of the first conductivity type formed in said first well; and, wherein said first conductivity type is P-type and said second conductivity type is N-type, and wherein the device further comprising: a pair of first MOS field effect transistors of P-type formed on the surface of said first well of N-type; a pair of second MOS field effect transistors of N-type formed on the surface of said second well of P-type; and said four MOS field effect transistors being connected in a NAND circuit.
Claim 2
Dependent Claim
121 words
A semiconductor device having a semiconductor substrate supplied with a fluctuating voltage comprising: said semiconductor substrate of a first conductivity type; a first well of a second conductivity type formed in said semiconductor substrate; a second well of the first conductivity type formed in said first well; and, wherein said first conductivity type is P-type and said second conductivity type is N-type, and wherein the device further comprising: a pair of first MOS field effect transistors of P-type formed on the surface of said first well of N-type; a pair of second MOS field effect transistors of N-type formed on the surface of said second well of P-type; and said four MOS field effect transistors being connected in a NAND circuit.
Claim 3
Dependent Claim
27 words
A semiconductor device according to claim 1 wherein said second well is connected to a ground potential and said first well is connected to a power source.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |