Abstract A highly integrated semiconductor memory device, such as a DRAM, is provided with a unique triple-well structure which results in reduced junction capacitance of transistors and a smaller body effect. The semiconductor memory device comprises first and second wells of a first conductivity type and a third well of a second conductivity type formed in a semiconductor substrate of the first conductivity type. The first well is formed in the third well and the first well and the second well are connected to receive a ground level Vss well bias voltage and a negative level V BB well bias voltage, respectively. A plurality of MOS transistors of the first conductivity type are formed in the third well and at least two series-connected MOS transistors of the second conductivity type are formed in the first well. A plurality of MOS transistors of the second conductivity type and a plurality of memory cells are also formed in the second well.
A semiconductor memory device comprising: first and second wells of a first conductivity type and a third well of a second conductivity type formed in a semiconductor substrate of said first conductivity type; said first well being formed in said third well and said first well and said second well being connected to receive a first well bias voltage and a second well bias voltage, respectively; at least one MOS transistor of said first conductivity type formed in said third well; at least two series-connected MOS transistors of said second conductivity type formed in said first well; and at least one MOS transistor of said second conductivity type and at least one memory cell formed in said second well.
Claim 2
Dependent Claim
119 words
A semiconductor memory device comprising: first and second wells of a first conductivity type and a third well of a second conductivity type formed in a semiconductor substrate of said first conductivity type; said first well being formed in said third well and said first well and said second well being connected to receive a first well bias voltage and a second well bias voltage, respectively; at least one MOS transistor of said first conductivity type formed in said third well; at least two series-connected MOS transistors of said second conductivity type formed in said first well; and at least one MOS transistor of said second conductivity type and at least one memory cell formed in said second well.
Claim 3
Dependent Claim
36 words
A semiconductor memory device as claimed in claim 1, wherein said first, second and third wells are for coupling to a ground voltage supply, to a negative voltage supply, and to a power voltage supply, respectively.
Claim 4
Dependent Claim
24 words
A semiconductor memory device as claimed in claim 1, wherein each of said at least one memory cell comprises a transistor and a capacitor.