Semiconductor device having different impurity concentration wells

Claim 2

A semiconductor device comprising: a semiconductor substrate; a first well of a first conductivity type formed in said semiconductor substrate; a second well of the first conductivity type formed adjacent to said first well in said semiconductor substrate such that nothing intervenes between said first and second wells except said semiconductor substrate, said second well having a surface impurity concentration lower than that of said first well; means for supplying a first potential to each of said first and second wells; a memory cell structure formed in said first well; and a transistor structure having a power supply voltage and being formed in said second well to function in combination with said memory cell structure, said memory cell structure having a power supply voltage smaller than said power supply voltage of said transistor structure.

Claim 3

A semiconductor device according to claim 1, wherein said semiconductor substrate is of a second conductivity type different from said first conductivity type, and wherein the device further comprises: a third well of the second conductivity type formed separately from said semiconductor substrate in said second well, a PN junction formed between said third well and said second well, said PN junction being reverse biased by a potential difference between the potential of said semiconductor substrate and the potential of said third well to electrically isolate said third well form the other wells, wherein at least part of said transistor structure is formed in said third well.

Claim 4

A semiconductor device according to claim 2, further comprising: voltage supplying means for supplying a potential to said third well different from the potential of said semiconductor substrate.

Claim 5

A semiconductor device according to claim 3, wherein at least one well of the second conductivity type is formed in said second well, and each of said second conductivity type wells is supplied with an independent potential.

Claim 6

A semiconductor device according to claim 3, wherein the potential of said semiconductor substrate is applied from an external power source of the semiconductor device, and said voltage supplying means includes a voltage converting circuit for converting the output potential of said external source to a different potential.

Claim 7

A semiconductor device according to claim 3, wherein said voltage converting circuit is formed in a well formed separately from said first well and said second well in said semiconductor substrate.

Claim 8

A semiconductor device according to claim 2, further comprising: a fourth well of the first conductivity type formed separately from said first well and said second well in said semiconductor substrate, said fourth well having an impurity concentration lower than that of said first well and having a second transistor structure formed therein to be used in combination with said memory cell structure.

Claim 9

A semiconductor device according to claim 7, wherein the impurity concentration of said fourth well is set lower than that of said first well and higher than that of said second well.

Claim 10

A semiconductor device according to claim 3, further comprising: a fifth well of the second conductivity type formed in said semiconductor substrate, said fifth well being formed separately from said first well, said second well, and said fourth well, wherein a third transistor structure used in combination with said memory cell structure is being formed in said fifth well.

Claim 11

A semiconductor device according to claim 9, wherein said third well has a majority carrier concentration lower than that of said fifth well.

Claim 12

A semiconductor device according to claim 7, wherein the majority carrier concentration of said fourth well is set lower than that of said first well.

Claim 13

A semiconductor device according to claim 7, wherein the impurity concentration of said first well is set higher than that of said fourth well by doping and diffusing an impurity of the first conductivity into said first well.

Claim 14

A semiconductor device according to claim 1, further including a well of the second conductivity type formed separately from the other wells in said semiconductor substrate and wherein said first well is formed in said well of the second conductivity type.

Claim 15

A semiconductor device according to claim 1, wherein said memory cell has a DRAM structure, and includes a memory cell capacitor section and an MOS transistor section of charging and discharging said memory cell capacitor section.

Claim 16

A semiconductor device according to claim 14, wherein said memory cell capacitor section has a trench cell structure.

Claim 17

A semiconductor device according to claim 14, wherein said memory cell capacitor section has a stacked cell structure.

Claim 18

A semiconductor device according to claim 14, wherein said memory cell capacitor section has a stacked trench cell structure.

Claim 19

A semiconductor device according to claim 14, wherein said memory cell capacitor section has a planar cell structure.

Claim 20

A semiconductor device according to claim 1, wherein an impurity of the second conductivity type is injected and diffused into a high impurity concentration region of a first conductivity type region.

Claim 21

A semiconductor device according to claim 1, wherein said memory cell structure has a SRAM structure.

Claim 22

A semiconductor device according to claim 1, wherein the majority carrier concentration of said second well is set lower than that of said first well.

Claim 23

A semiconductor device according to claim 1, wherein the impurity concentration of said first well is set higher than that of said second well by doping and diffusing an impurity of the first conductivity type into said first well.

Claim 24

A semiconductor device according to claim 1, wherein said semiconductor substrate is of a second conductivity type different from said first conductivity type and wherein the device further comprises: a third well of the second conductivity type formed separately from said semiconductor substrate in said second well, a PN junction formed between said second well and said semiconductor substrate and reverse biased by a potential difference between the potential of said semiconductor substrate and the potential of said third well to electrically isolate said third well from the other wells, wherein at least part of said transistor structure is formed in said third well.

Claim 25

A semiconductor device according to claim 23, further comprising: a fourth well of the first conductivity type formed separately from said first well and said second well in said semiconductor substrate, said fourth well having an impurity concentration lower than that of said first well and having a second transistor structure formed therein to be used in combination with said memory cell structure.

Claim 26

A semiconductor device according to claim 24, wherein the majority carrier concentration of said fourth well is set lower than that of said first well by doping and diffusing an impurity of the second conductivity type into said fourth well.

Claim 27

A semiconductor device according to claim 24, wherein the impurity concentration of said first well is set higher than that of said fourth well by doping and diffusing an impurity of the first conductivity type into said first well.

Claim 28

A semiconductor device according to claim 24, further comprising: a fifth well of the second conductivity type formed in said semiconductor substrate separately from said first well, said second well, and said fourth well, and a third transistor being formed in said fifth well to be used in combination with said memory cell structure.

Claim 29

A semiconductor device according to claim 24, wherein said fourth well has an impurity concentration lower than that of said first well and higher than that of said second well.

Claim 30

A semiconductor device according to claim 28, wherein said third well has a majority carrier concentration lower than that of said fifth well.

Claim 31

A semiconductor device according to claim 23, further comprising voltage supplying means for supplying a potential to said third well different from the potential of said semiconductor substrate.

Claim 32

A semiconductor device according to claim 30, wherein at least one well of said second conductivity type is formed in said second well, and each well of said second conductivity type is supplied with an independent potential.

Claim 33

A semiconductor device according to claim 30, wherein a potential is applied to the semiconductor substrate from an external power source and wherein said voltage supplying means includes a voltage converting circuit for converting the output potential of the external power source to a different potential.

Claim 34

A semiconductor device according to claim 32, wherein said voltage converting circuit is formed in a well separately from said first well and said second well in said semiconductor substrate.

Claim 35

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a memory cell well of a second conductivity type different from said first conductivity type and formed in said semiconductor substrate; a DRAM memory cell structure formed in said memory cell well; a first peripheral cell structure formed in said memory cell well; a first peripheral circuit well of the second conductivity type formed adjacent to said memory cell in said semiconductor substrate such that nothing intervenes between said memory cell well and first peripheral circuit well except said semiconductor substrate, said first peripheral circuit well having an impurity concentration lower than said impurity concentration of said memory cell well; means for supplying a first potential to each of said memory cell well and first peripheral circuit well; an internal well of said first conductivity type formed in said first peripheral circuit well to include a first MOS transistor structure to be used in combination with said memory cell structure; a second peripheral circuit well formed separately from said memory cell well in said semiconductor substrate to include a second MOS transistor structure to be used in combination with said memory cell structure, said second peripheral circuit well having an impurity concentration lower than that of said memory cell well; and a third peripheral circuit well formed separately from said memory cell well in said semiconductor substrate to include a third MOS transistor structure to be used in combination with said memory cell structure.

Claim 36

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a memory cell well of a second conductivity type different from said first conductivity type and formed in said semiconductor substrate; a DRAM memory cell structure formed in said memory cell well; a first peripheral cell structure formed in said memory cell well; a first peripheral circuit well of the second conductivity type formed adjacent to said memory cell in said semiconductor substrate such that nothing intervenes between said memory cell well and first peripheral circuit well except said semiconductor substrate, said first peripheral circuit well having an impurity concentration lower than said impurity concentration of said memory cell well; means for supplying a first potential to each of said memory cell well and first peripheral circuit well; an internal well of said first conductivity type formed in said first peripheral circuit well to include a first MOS transistor structure to be used in combination with said memory cell structure; a second peripheral circuit well formed separately from said memory cell well in said semiconductor substrate to include a second MOS transistor structure to be used in combination with said memory cell structure, said second peripheral circuit well having an impurity concentration lower than that of said memory cell well; and a third peripheral circuit well formed separately from said memory cell well in said semiconductor substrate to include a third MOS transistor structure to be used in combination with said memory cell structure.

Claim 37

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a memory cell well of a second conductivity type formed in said semiconductor substrate; a DRAM memory cell structure formed in said memory cell well; a first peripheral circuit well of the second conductivity type formed adjacent to said memory cell well in said semiconductor substrate such that nothing intervenes between said first and second wells except said semiconductor substrate, the impurity concentration of said first peripheral circuit well being set lower than that of said memory cell well; means for supplying a first potential to each of said memory cell well and first peripheral circuit well; an internal well of said first conductivity type formed in said first peripheral circuit well to include a first MOS transistor structure to be used in combination with said memory well structure; a second peripheral circuit well formed separately from said memory cell well in said semiconductor substrate to include a second MOS transistor structure to be used in combination with said memory cell structure, the impurity concentration of said second peripheral circuit well being set higher than that of said internal well formed at said first peripheral circuit well.

Claim 38

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a memory cell well of a second conductivity type formed in said semiconductor substrate; a DRAM memory cell structure formed in said memory cell well; a first peripheral circuit well of the second conductivity type formed adjacent to said memory cell well in said semiconductor substrate such that nothing intervenes between said first and second wells except said semiconductor substrate, the impurity concentration of said first peripheral circuit well being set lower than that of said memory cell well; means for supplying a first potential to each of said memory cell well and first peripheral circuit well; an internal well of said first conductivity type formed in said first peripheral circuit well to include a first MOS transistor structure to be used in combination with said memory well structure; a second peripheral circuit well formed separately from said memory cell well in said semiconductor substrate to include a second MOS transistor structure to be used in combination with said memory cell structure, the impurity concentration of said second peripheral circuit well being set higher than that of said internal well formed at said first peripheral circuit well.