Semiconductor memory having trench capacitor formed with sheath electrode

Claim 2

A semiconductor memory comprising memory cells each of which is constructed of a trench type charge storage capacitor formed within a semiconductor substrate of a first conductivity type, a switching transistor, and a heavily doped embedded impurity region formed at the bottom of said trench capacitor and within said semiconductor substrate, and wherein each trench capacitor is comprised of: a first capacitor electrode including a sheath-shaped structure having a bottom portion which is electrically connected with the semiconductor substrate via said heavily doped embedded impurity region and which has a sideward periphery covered with an insulator film thereby forming an insulator barrier with said semiconductor substrate and a second capacitor electrode having a part which is buried inside said sheath-shaped first electrode through a dielectric film of said capacitor and another part which is electrically connected with an impurity doped layer of a second conductivity type opposite to said first conductivity type formed in a surface region of said semiconductor substrate to function as one of a source and drain regions of said transistor.

Claim 3

A semiconductor memory according to claim 1, wherein a portion for the electrical connection between said second capacitor electrode and one of said source and drain regions of said transistor exists at an inner part of said substrate below a surface of said substrate, and a surface of said trench capacitor is covered with an insulator produced by oxidizing or nitriding the second electrode of said capacitor.

Claim 4

A semiconductor memory according to claim 1, further comprising a CMOS peripheral circuit, a p-channel MOS transistor of which is formed in an n-well region and an n-channel MOS transistor of which is formed in a p-well region.

Claim 5

A semiconductor memory according to claim 1, wherein said sheath-shaped first electrode is made of polycrystalline silicon.

Claim 6

A semiconductor memory according to claim 1, wherein at least a part of said heavily doped region which is within said substrate is led out to a front surface of said substrate or a rear surface thereof.

Claim 7

A semiconductor memory comprising memory cells, each of which is constructed of a trench type charge storage capacitor formed within a semiconductor substrate of a first conductivity type, a switching transistor, and a heavily doped region of a second conductivity type, opposite said first conductivity type, which is formed within said semiconductor substrate and which has a doping concentration greater than that in said semiconductor substrate, and wherein in each memory cell the charge storage capacitor is comprised of: a first electrode of said capacitor which has a sheath-shaped structure formed in a groove which is provided in a surface region of said semiconductor substrate and which is electrically connected in a bottom portion thereof with said heavily doped region, said first electrode of a sheath-shaped structure having a periphery which is covered with an insulator film except for the electrically connected part with said heavily doped region; a second electrode of said capacitor having a part which is buried inside said first sheath-shaped electrode through a dielectric film of said capacitor and another part which is electrically connected with an impurity doped layer of said second conductivity type formed in a surface region of said semiconductor substrate to function as one of a source and drain regions of said switching transistor; and a highly-doped diffused layer of said first conductivity type embedded in said semiconductor substrate between the surface thereof and said heavily doped region and formed so as to be in contact with a portion of said insulator film such that an unwanted vertical MOS transistor effected by said heavily doped region and said first sheath-shaped electrode, acting as a drain and gate, respectively, would be prevented from switching to an on condition.

Claim 8

A semiconductor memory comprising memory cells, each of which is constructed of a trench type charge storage capacitor formed within a semiconductor substrate of a first conductivity type, a switching transistor, and a heavily doped region of a second conductivity type, opposite said first conductivity type, which is formed within said semiconductor substrate and which has a doping concentration greater than that in said semiconductor substrate, and wherein in each memory cell the charge storage capacitor is comprised of: a first electrode of said capacitor which has a sheath-shaped structure formed in a groove which is provided in a surface region of said semiconductor substrate and which is electrically connected in a bottom portion thereof with said heavily doped region, said first electrode of a sheath-shaped structure having a periphery which is covered with an insulator film except for the electrically connected part with said heavily doped region; a second electrode of said capacitor having a part which is buried inside said first sheath-shaped electrode through a dielectric film of said capacitor and another part which is electrically connected with an impurity doped layer of said second conductivity type formed in a surface region of said semiconductor substrate to function as one of a source and drain regions of said switching transistor; and a highly-doped diffused layer of said first conductivity type embedded in said semiconductor substrate between the surface thereof and said heavily doped region and formed so as to be in contact with a portion of said insulator film such that an unwanted vertical MOS transistor effected by said heavily doped region and said first sheath-shaped electrode, acting as a drain and gate, respectively, would be prevented from switching to an on condition.

Claim 9

A semiconductor memory according to claim 6, wherein a portion for the electrical connection between said second electrode of said capacitor and one of said source and drain regions of said transistor exists at an inner part of said substrate below a surface of said substrate, and a surface of said trench capacitor is covered with an insulator produced by oxidizing or nitriding the second electrode of said capacitor.

Claim 10

A semiconductor memory according to claim 6, further comprising a CMOS peripheral circuit, a p-channel MOS transistor of which is formed in an n-well region and an n-channel MOS transistor of which is formed in a p-well region.

Claim 11

A semiconductor memory according to claim 6, wherein said first sheath-shaped capacitor electrode is made of polycrystalline silicon.

Claim 12

A semiconductor memory according to claim 6, wherein a voltage of 1/2 V cc is applied to said heavily doped region within said substrate, whereby said sheath electrode is operated as a 1/2 V cc plate electrode.

Claim 13

A semiconductor memory according to claim 8, wherein a portion for the electrical connection between said second electrode of said capacitor and one of said source and drain regions of said transistor exists at an inner part of said substrate below a surface of said substrate, and a surface of said trench capacitor is covered with an insulator produced by oxidizing or nitriding the second electrode of said capacitor.

Claim 14

A semiconductor memory according to claim 6, wherein in at least one of said memory cells the sheath-shaped electrode is led out to a surface of said substrate, so that a voltage can be applied to said heavily doped region within said substrate through the lead-out electrode.

Claim 15

A semiconductor memory according to claim 6, wherein at least a part of said heavily doped region within said substrate is led out to a front surface of said substrate or a rear surface thereof.

Claim 16

A semiconductor memory according to claim 6, wherein said heavily doped region is an impurity layer which is formed within said semiconductor substrate in at least a part of the surrounding region below said groove.

Claim 17

A dynamic random access memory comprising memory cells, each having a MOS transfer switch in series with a trench type charge storage capacitor which is formed in a semiconductor substrate of a first conductivity type in a groove region thereof having a bottom portion in electrical contact with a heavily doped embedded region, said capacitor including a first electrode having a sheath-shaped structure of a predetermined thickness which is vertically formed in said groove provided in a main surface region of said semiconductor substrate, said sheath-shaped structure having a bottom portion which is electrically connected with said heavily doped embedded region and having a periphery which is covered with an insulator film except for the portion in electrical contact with said heavily doped embedded region, and a second electrode having a first part formed in said groove inside said sheath-shaped electrode and separated therefrom by a dielectric film of said capacitor and a second part which is electrically connected with one of a pair of impurity doped regions of a second conductivity type opposite to said first conductivity type formed in a surface region of said semiconductor substrate which functions as a source region of a memory cell MOS switching transistor.

Claim 18

A dynamic random access memory comprising memory cells, each having a MOS transfer switch in series with a trench type charge storage capacitor which is formed in a semiconductor substrate of a first conductivity type in a groove region thereof having a bottom portion in electrical contact with a heavily doped embedded region, said capacitor including a first electrode having a sheath-shaped structure of a predetermined thickness which is vertically formed in said groove provided in a main surface region of said semiconductor substrate, said sheath-shaped structure having a bottom portion which is electrically connected with said heavily doped embedded region and having a periphery which is covered with an insulator film except for the portion in electrical contact with said heavily doped embedded region, and a second electrode having a first part formed in said groove inside said sheath-shaped electrode and separated therefrom by a dielectric film of said capacitor and a second part which is electrically connected with one of a pair of impurity doped regions of a second conductivity type opposite to said first conductivity type formed in a surface region of said semiconductor substrate which functions as a source region of a memory cell MOS switching transistor.

Claim 19

A dynamic random access memory according to claim 15, wherein said semiconductor substrate has a doping concentration which is lower than that in said heavily doped region.

Claim 20

A dynamic random access memory according to claim 16, wherein said heavily doped embedded region is of said first conductivity type.

Claim 21

A dynamic random access memory according to claim 17, further including a lead-out electrode of said capacitor first electrode vertically formed in said semiconductor substrate near said main surface region so as to facilitate contact between said heavily-doped embedded region and a lead wire surface layer, said lead-out electrode extending into the semiconductor substrate to a depth corresponding to that of said sheath-shaped structure.

Claim 22

A semiconductor memory according to claim 15, wherein a portion for the electrical connection between said second electrode of the capacitor and said source region of said transistor exists at an inner part of said substrate below a surface of said substrate, and a surface of said trench capacitor is covered with an insulator produced by oxidizing or nitriding the second electrode of said capacitor.

Claim 23

A dynamic random access memory comprising memory cells, each having a MOS transfer switch in series with a trench type charge storage capacitor which is formed in a semiconductor substrate of a first conductivity type in a groove region thereof having a bottom portion in electrical contact with a heavily doped embedded region having greater doping concentration than that of said semiconductor substrate and of a second conductivity type, opposite said first conductivity type, said capacitor including: a first electrode having a sheath-shaped structure of a predetermined thickness which is vertically formed in said groove provided in a main surface region of said semiconductor substrate, said sheath-shaped structure having a bottom portion which is electrically connected with said heavily doped embedded region and having a periphery which is covered with an insulator film except for the portion in electrical contact with said heavily doped embedded region; a second electrode having a first part formed in said groove inside said sheath-shaped electrode and separated therefrom by a dielectric film of said capacitor and a second part which is electrically connected with one of a pair of impurity doped regions of said second conductivity type formed in a main surface region of said semiconductor substrate which functions as a source region of a memory cell MOS switching transistor; a lead-out electrode of said capacitor first electrode which is vertically formed in said semiconductor substrate near said main surface region so as to facilitate contact between said heavily-doped embedded region and a lead wire surface layer, said lead-out electrode extending into the semiconductor substrate to a depth corresponding to that of said sheath-shaped structure; and a highly doped diffused layer of said first conductivity type embedded in said semiconductor substrate between the surface thereof and said heavily doped embedded region and formed so as to be in contact with a portion of said insulator film such that an unwanted vertical MOS transistor effected by said heavily doped region and said first electrode, acting as a drain and gate, respectively, would be prevented from switching to an on condition.

Claim 24

A dynamic random access memory comprising memory cells, each having a MOS transfer switch in series with a trench type charge storage capacitor which is formed in a semiconductor substrate of a first conductivity type in a groove region thereof having a bottom portion in electrical contact with a heavily doped embedded region having greater doping concentration than that of said semiconductor substrate and of a second conductivity type, opposite said first conductivity type, said capacitor including: a first electrode having a sheath-shaped structure of a predetermined thickness which is vertically formed in said groove provided in a main surface region of said semiconductor substrate, said sheath-shaped structure having a bottom portion which is electrically connected with said heavily doped embedded region and having a periphery which is covered with an insulator film except for the portion in electrical contact with said heavily doped embedded region; a second electrode having a first part formed in said groove inside said sheath-shaped electrode and separated therefrom by a dielectric film of said capacitor and a second part which is electrically connected with one of a pair of impurity doped regions of said second conductivity type formed in a main surface region of said semiconductor substrate which functions as a source region of a memory cell MOS switching transistor; a lead-out electrode of said capacitor first electrode which is vertically formed in said semiconductor substrate near said main surface region so as to facilitate contact between said heavily-doped embedded region and a lead wire surface layer, said lead-out electrode extending into the semiconductor substrate to a depth corresponding to that of said sheath-shaped structure; and a highly doped diffused layer of said first conductivity type embedded in said semiconductor substrate between the surface thereof and said heavily doped embedded region and formed so as to be in contact with a portion of said insulator film such that an unwanted vertical MOS transistor effected by said heavily doped region and said first electrode, acting as a drain and gate, respectively, would be prevented from switching to an on condition.

Claim 25

A semiconductor memory according to claim 20, wherein a voltage of 1/2 V cc is applied to said heavily doped region within said substrate, whereby said sheath-shaped electrode is operated as a 1/2 V cc plate electrode.

Claim 26

A semiconductor memory comprising memory cells each of which is constructed of a trench type charge storage capacitor formed within a semiconductor substrate of a first conductivity type, a switching transistor, and a heavily doped embedded region which is formed at the bottom of said trench capacitor and within said semiconductor substrate and wherein each trench capacitor is comprised of: a first capacitor electrode including a sheath-shaped structure which is formed in a groove provided in said semiconductor substrate through a principal surface thereof, said sheath-shaped structure having a bottom portion which is electrically connected with said heavily doped embedded region, and a sideward periphery which is covered with an insulator film which forms an insulator barrier with said semiconductor substrate; and a second capacitor electrode including a part which is buried inside the sheath-shaped first capacitor electrode through a dielectric film of said capacitor and another part which is electrically connected with an impurity doped layer of a second conductivity type, opposite to said first conductivity type, formed in a surface region of said semiconductor substrate near said principal surface to function as one of a source and drain regions of said switching transistor.

Claim 27

A semiconductor memory comprising memory cells each of which is constructed of a trench type charge storage capacitor formed within a semiconductor substrate of a first conductivity type, a switching transistor, and a heavily doped embedded region which is formed at the bottom of said trench capacitor and within said semiconductor substrate and wherein each trench capacitor is comprised of: a first capacitor electrode including a sheath-shaped structure which is formed in a groove provided in said semiconductor substrate through a principal surface thereof, said sheath-shaped structure having a bottom portion which is electrically connected with said heavily doped embedded region, and a sideward periphery which is covered with an insulator film which forms an insulator barrier with said semiconductor substrate; and a second capacitor electrode including a part which is buried inside the sheath-shaped first capacitor electrode through a dielectric film of said capacitor and another part which is electrically connected with an impurity doped layer of a second conductivity type, opposite to said first conductivity type, formed in a surface region of said semiconductor substrate near said principal surface to function as one of a source and drain regions of said switching transistor.

Claim 28

A semiconductor memory according to claim 22, wherein a voltage of 1/2 V cc is applied to said heavily doped region within said substrate, whereby said sheath-shaped first electrode is operated as a 1/2 V cc plate electrode.

Claim 29

A semiconductor memory according to claim 22, wherein in at least one of said memory cells the sheath-shaped electrode is led out to a principal surface of said substrate, so that a voltage can be applied to said heavily doped region within said substrate through the lead-out electrode.

Claim 30

A semiconductor memory according to claim 22, wherein said heavily doped embedded region is of the second conductivity type; and wherein there is further included an impurity layer of the first conductivity type which is formed within said semiconductor substrate in at least a part of a surrounding region of said groove between said bottom portion of said sheath-shaped structure and said surface region of said semiconductor substrate.