Semiconductor memory device with information storage vertical trench capacitor and method of manufacturing the same

Claim 2

A semiconductor memory device which includes a substrate of semiconductor material, and a plurality of programmable memory cells formed at the substrate, each memory cell containing at least one switching transistor formed in the substrate and isolated from adjacent electric components at the substrate by a trench of a given depth formed in the substrate at the side of the switching transistor, the trench having an inner surface coated with an insulator, and one storage capacitor connected to the switching transistor and formed at the trench at the side of the associated switching transistor, wherein the improvement comprises the above mentioned storage capacitor including a first vertical electrode provided on the insulator coated inner side wall of the trench and laterally connected to one conductive region of the switching transistor through a opening formed in the insulator coating on the inner side wall of the trench, an vertical insulative layer provided on the first vertical electrode, and a second vertical electrode provided on the vertical insulative layer.

Claim 3

A semiconductor memory device claimed in Claim 1 wherein the opening is formed on the upper edge of the insulator coating on the trench side wall, and is filled with a portion of the first vertical electrode so that the first vertical electrode is ohmic-contacted to the one conductive region of the switching transistor through a region of the substrate adjacent to the opening.

Claim 4

A semiconductor memory device claimed in Claim 2 wherein the trench is formed to substantially surround the switching transistor, and wherein the storage capacitor is formed in a trench portion adjacent to the above mentioned conductive region of the switching transistor.

Claim 5

A semiconductor memory device claimed in Claim 3 wherein the trench is of a rectangular shape in a plan view and wherein the storage capacitor is formed to extend over a substantial entire wall of one side of the rectangular shaped trench adjacent to the above mentioned conductive region of .the switching transistor.

Claim 6

A semiconductor memory device claimed in Claim 4 wherein the above mentioned one side portion of the trench is completely refilled with the first and second vertical electrodes and the vertical insulative layer which constitute the storage capacitor.

Claim 7

A semiconductor memory device claimed in Claim 1 wherein at least one pair of adjacent memory cells include a pair of switching transistors which are isolated from each other by the trench formed between the one pair of transistors, and wherein the first vertical electrode is provided on each of opposite insulator coated side walls of the trench and is electrically connected to one conductive region of the adjacent switching transistor through a opening formed in the insulator coating on each inner side wall of the trench, the vertical insulative layer being provided on each of the first vertical electrodes in the same trench, and a common second electrode being provided between the vertical insulative layers, whereby one pair of vertical storage capacitors are formed in the trench between the one pair of switching transistors and each of the capacitors is associated to an adjacent one of the two transistors.

Claim 8

A semiconductor memory device claimed in Claim 6 wherein the opening is formed on the upper edge of the insulator coating on each trench side wall, and is filled with a portion of the first vertical electrode so that each first vertical electrode is ohmic-contacted to the one conductive region of the adjacent switching transistor through a region of the substrate adjacent to the opening.

Claim 9

A semiconductor memory device claimed in Claim 7 wherein the trench between the one pair of switching transistors is completely refilled with the first and second vertical electrodes and the vertical insulative layers which constitute the above mentioned one pair of storage capacitors, and wherein each of the first vertical electrodes has a thickness not greater than one-third of the gap of the trench.

Claim 10

A semiconductor memory device claimed in Claim 1 wherein each switching transistor is an insulated-gate field effect transistor, one of the source and drain regions of the field effect transistor being contacted to the first vertical electrode through the opening formed in the insulator coating on the side wall of the trench.

Claim 11

A semiconductor memory device claimed in Claim 1 wherein the substrate of semiconductor material is of one conduction type, and wherein the first and second vertical electrodes are formed from a semiconductor material of the conduction type opposite to that of the substrate.

Claim 12

A semiconductor memory device claimed in Claim 1 wherein the substrate of semiconductor material is a p-type single-crystalline silicon substrate, and wherein the first and second vertical electrodes are formed of n-type polycrystalline silicon which is doped with material selected from a group consisting of phosphorus and arsenic .

Claim 13

A semiconductor memory device claimed in Claim 11 wherein the insulator coating on the side wall of the trench is formed of silicon dioxide, and wherein the vertical insulative layer between the first and second vertical electrodes is constituted of a silicon dioxide layer formed on the first vertical electrode and a silicon nitride layer deposited on the silicon dioxide layer.

Claim 14

A semiconductor memory device claimed in Claim 12 wherein each switching transistor is an insulated-gate field effect transistor, one of the source and drain regions of the field effect transistor being contacted to the first vertical electrode through the opening formed in the insulator coating on the side wall of the trench.

Claim 15

A semiconductor memory device claimed in Claim 13 further including a plurality of column lines and a plurality of row lines intersecting the column lines and wherein the plurality of memory cells are disposed at the intersections . of the column lines and the row lines in such a manner that each switching field effect transistor has a gate connected to the corresponding one of the row lines, and the other of the source and drain regions is connected to the corresponding one of the column.

Claim 18

A method claimed in Claim 15 wherein before the switching transistor is formed, the substrate is heated so that a portion of impurities contained in the first vertical electrode is diffused to the substrate through the opening of the insulator coating on the trench inner wall so as to form a contact region in the substrate adjacent to an upper portion of the first vertical electrode, so that the diffused contact region will be continuous to the one conductive region of the switching when it is formed.

Claim 19

A method claimed in Claim 15 wherein the step of forming the opening includes: filling the trench with a resist material while leaving the side wall of the upper edge portion of the trench in an exposed condition; forming on the upper surface of the substrate a layer of resist material having an opening corresponding to and not smaller than the trench so as to leave the upper edge portion of the trench in an exposed condition; and removing the exposed insulator film on the trench side wall by using as the mask the resist material in the trench and on the substrate upper surface, so that the substrate is exposed at the side wall of the upper edge portion of the trench.

Claim 20

A method claimed in Claim 17 wherein the filling of the resist material of the trench and the formation of the resist material layer leaving the side wall of the trench upper edge portion in the exposed condition are achieved by: depositing the resist material on the substrate to perfectly fill the trench and to coat the overall upper surface of the substrate; depositing an insulative material on the resist coating; forming on the insulative material layer a resist pattern having an opening in alignment with the trench and not smaller than the trench; removing the insulative material layer by using the resist pattern as a mask so as to form an opening in the insulative material layer corresponding to the opening of the second resist film; and removing the resist pattern and the resist materials by using the insulative material layer as a mask, so as to perfectly remove the resist pattern and at the same time to remove the resist material on and in the trench is removed with the result that the trench is filled with the resist material to leave the side wall of the trench upper edge portion in the exposed condition and the substrate is covered with the resist coating having the opening corresponding to the trench opening to leave the trench.

Claim 21

A method claimed in Claim 18 wherein before the switching transistor is formed, the substrate is heated so that a portion of impurities contained in the first vertical electrode is diffused to the substrate through the opening of the insulator coating on the trench inner wall so as to form a contact region in the substrate adjacent to an upper portion of the first vertical electrode, so that the contact region will be continuous to the one conductive region of the switching transistor when it is formed in the substrate.

Claim 22

A method claimed in Claim 15 wherein the substrate is a single-crystalline silicon substrate and wherein the step of forming the trench includes: forming a first silicon dioxide coating, a silicon nitride coating and a second silicon dioxide coating on the upper surface of the substrate in the mentioned order; depositing a resist pattern on the second silicon dioxide coating excluding an area in which a trench is to be formed; etching the second silicon dioxide coating, the silicon nitride coating and the first silicon dioxide coating by using the resist pattern as a mask; also etching the silicon substrate by using the resist pattern and the second silicon dioxide coating as a mask to form a trench in the silicon substrate; removing the second silicon dioxide coating; and thermally oxidizing the inner surface of the trench thus formed by using the silicon nitride coating as oxidation protecting mask, so that the inner surface of the trench is coated with the silicon dioxide.

Claim 23

A method claimed in Claim 20 wherein the step of forming the opening in the insulator coating on the trench side wall includes: depositing a resist material on the substrate to perfectly fill the silicon dioxide coated trench and to cover the upper surface of the silicon nitride coating: depositing an insulative material on the resist cover; forming on the insulative material layer a resist pattern having an opening in alignment with the trench and not smaller than the trench; removing the insulative material layer by using the resist pattern as a mask so as to form an opening in the insulative material layer corresponding to the opening of the second resist film; removing the resist pattern and the resist materials by using the insulative material layer as a mask, to perfect remove the resist pattern and at the same time to remove the resist material on and in the trench so that the trench is filled with the resist material to leave the side wall of the trench upper edge portion in the exposed condition and the substrate is covered with the resist coating having the opening corresponding to the trench; and removing the exposed silicon dioxide coating on the trench side wall by using as the mask the remaining resist material in the trench and on the substrate upper surface, so that the substrate is exposed at the side wall of the upper edge portion of the trench.

Claim 24

A method claimed in Claim 21 wherein the removal of the resist pattern and the resist material by using the insulative material layer as the mask is achieved by a reactive sputter etching.

Claim 25

A method claimed in Claim 21 wherein the step of forming the first vertical electrode includes: removing the remaining insulative material layer on the substrate and the remaining resist material; depositing on the substrate a polycrystalline silicon of the conduction type opposite to that of the substrate so as to form on the side wall of the trench a polycrystalline silicon layer which has a thickness not greater than one-third of the gap of the trench and which is directly contacted to the exposed substrate through the opening formed in the upper edge of the silicon dioxide coating on the trench wall; and removing the polycrystalline silicon on the upper surface of the substrate and on the bottom of the trench by a reactive sputter etching so that a first vertical polycrystalline silicon layer remains only on each side wall of the trench so as to form the first vertical electrode.

Claim 26

A method claimed in Claim 23 wherein the provision of the insulative layer on the first vertical electrode is realized by thermally oxidizing the surface of the first vertical polycrystalline silicon layer, and then depositing a silicon nitride film on the substrate and the oxidized surface of the first polycrystalline silicon layer.

Claim 27

A method claimed in Claim 24 wherein the step of forming the second vertical electrode includes: depositing on the surface of the substrate a polycrystalline silicon of the conduction type opposite to that of the substrate so as to perfectly fill the remaining space of the trench; and removing the deposited polycrystalline silicon on the substrate so that the polycrystalline silicon remains only in the trench to constitute a second vertical polycrystalline layer for the second vertical electrode.

Claim 28

A method claimed in Claim 25 wherein before the switching transistor is formed, there is thermally oxidized an upper portion of the first and second vertical polycrystalline silicon layers by using the remaining silicon nitride coating on the substrate as oxidation protection mask, so that a silicon dioxide cover of a substantial thickness is formed on the top end of the first and second vertical polycrystalline silicon layers for protection of these vertical silicon layers, and at the same time, the impurities contained in the first vertical polycrystalline silicon layer are diffused to the substrate through the opening of the insulator coating on the trench inner wall so as to form a contact region in the substrate adjacent to an upper portion of the first vertical polycrystalline silicon whereby the contact region will be continuous to the one conductive region of the switching transistor when it is formed.

Claim 29

A method claimed in Claim 26 wherein the step of forming the switching transistor includes a formation of the above mentioned one conductive region of the switching transistor in an overlapped relation to the diffused contact region in the substrate continuous to the upper portion of the vertical polycrystalline silicon.

Claim 30

A semiconductor device comprising a substrate of semiconductor material having at least one insulator coated trench of a given depth, a transistor formed in the substrate adjacent to the trench, and a capacitor formed in the trench and electrically connected to the transistor, the capacitor including a first vertical electrode provided on the insulator coated inner side wall of the trench and electrically connected to one conductive region of the transistor, an vertical insulative layer provided on the first vertical electrode, and a second vertical electrode provided on the vertical insulative layer.

Claim 31

A semiconductor device comprising a substrate of semiconductor material having at least one insulator coated trench of a given depth, a transistor formed in the substrate adjacent to the trench, and a capacitor formed in the trench and electrically connected to the transistor, the capacitor including a first vertical electrode provided on the insulator coated inner side wall of the trench and electrically connected to one conductive region of the transistor, an vertical insulative layer provided on the first vertical electrode, and a second vertical electrode provided on the vertical insulative layer.

Claim 32

a semiconductor device claimed in Claim 28 wherein a opening is formed in an upper edge portion of the insulator coating on the side wall of the trench, the first vertical electrode being connected to the one conductive region of the transistor through the opening of the trench side wall insulator coating.

Claim 33

A semiconductor device claim 29 wherein the opening formed in trench side wall insulator coating is filled with a portion of the first vertical electrode so that the first vertical electrode is directly contacted to the one conductive region of the switching transistor.

Claim 34

A semiconductor device claimed in Claim 28 wherein the substrate of semiconductor material is of one conduction type, and wherein the first and second vertical electrodes are formed from a semiconductor material of the conduction type opposite to that of the substrate.

Claim 35

A semiconductor device claimed in Claim 28 wherein the substrate of semiconductor material is a p-type single-crystalline silicon substrate, and wherein the first and second vertical electrodes are formed of n-type polycrystalline silicon which is doped with material selected from a group consisting of phosphorus and arsenic.

Claim 36

A semiconductor device claimed in Claim 32 wherein the insulator coating on the side wall of the trench is formed of silicon dioxide, and wherein the vertical insulative layer between the first and second vertical electrodes is constituted of a silicon dioxide layer formed on the first vertical electrode and a silicon nitride layer deposited on the silicon dioxide layer.

Claim 37

A semiconductor device claimed in Claim 33 wherein each switching transistor is an insulated-gate field effect transistor, one of the source and drain regions of the field effect transistor being directly contacted to the first vertical electrode through the opening formed in the silicon dioxide coating on the side wall of the trench.