US5336913A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile semiconductor memory device and a method for fabricating the same
Assignee: Panasonic Holdings Corp
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Filing: 1992-07-17
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Granted: 1994-08-09
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Expires: 2012-07-17
Abstract
Abstract A long-life, electrically writable and erasable non-volatile semiconductor memory device is disclosed. The memory device is fabricated in the following steps. After forming a first gate insulating film on a semiconductor substrate, a window is opened in the first gate insulating film to expose a portion of the surface of the semiconductor substrate, using a two-step etching technique in which dry etching and wet etching are performed successively. The exposed portion of the semiconductor substrate not over-etched is selectively oxidized to form a tunnel insulating film (second gate insulating film) having edge portions resistant to dielectric breakdown. Thereafter, a floating gate, a third gate insulating film, and a control gate are formed sequentially. The floating gate is patterned in such a way as to cover the entire tunnel insulating film or cross only a portion of an edge of the tunnel insulating film. The stress caused to the tunnel insulating film as a result of the oxidation process for forming the third gate insulating film is relieved, providing the tunnel insulating film with resistance to dielectric strength.
Inventors
- 👤 Takao Kakiuchi
- 👤 Kazuo Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:11
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10B; H10B69/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
133 words
A non-volatile semiconductor memory device comprising: a silicon substrate having a source region and a drain region each formed by a diffusion layer; a first gate insulating film formed on said silicon substrate, said first gate insulating film having a window; a recess formed on said silicon substrate within said window, said recess having a bottom face and a plurality of side faces, said bottom face having a (100) plane, and said side faces each having a (110) plane; a second gate insulating film formed on said silicon substrate within said window; a floating gate formed on said first gate insulating film, said floating gate covering fully said second gate insulating film; a third gate insulating film formed on said floating gate; and a control gate formed on said third gate insulating film.
Claim 2
Dependent Claim
133 words
A non-volatile semiconductor memory device comprising: a silicon substrate having a source region and a drain region each formed by a diffusion layer; a first gate insulating film formed on said silicon substrate, said first gate insulating film having a window; a recess formed on said silicon substrate within said window, said recess having a bottom face and a plurality of side faces, said bottom face having a (100) plane, and said side faces each having a (110) plane; a second gate insulating film formed on said silicon substrate within said window; a floating gate formed on said first gate insulating film, said floating gate covering fully said second gate insulating film; a third gate insulating film formed on said floating gate; and a control gate formed on said third gate insulating film.
Claim 3
Dependent Claim
133 words
A non-volatile semiconductor memory device comprising: a silicon substrate having a source region and a drain region each formed by a diffusion layer; a first gate insulating film formed on said silicon substrate, said first gate insulating film having a window; a recess formed on said silicon substrate within said window, said recess having a bottom face and a plurality of side faces, said bottom face having a (100) plane, and said side faces each having a (111) plane; a second gate insulating film formed on said silicon substrate within said window; a floating gate formed on said first gate insulating film, said floating gate covering fully said second gate insulating film; a third gate insulating film formed on said floating gate; and a control gate formed on said third gate insulating film.
Claim 4
Dependent Claim
133 words
A non-volatile semiconductor memory device comprising: a silicon substrate having a source region and a drain region each formed by a diffusion layer; a first gate insulating film formed on said silicon substrate, said first gate insulating film having a window; a recess formed on said silicon substrate within said window, said recess having a bottom face and a plurality of side faces, said bottom face having a (100) plane, and said side faces each having a (111) plane; a second gate insulating film formed on said silicon substrate within said window; a floating gate formed on said first gate insulating film, said floating gate covering fully said second gate insulating film; a third gate insulating film formed on said floating gate; and a control gate formed on said third gate insulating film.
Claim 5
Dependent Claim
132 words
A non-volatile semiconductor memory device comprising: a silicon substrate having a source region and a drain region each formed by a diffusion layer; a first gate insulating film formed on said silicon substrate, said first gate insulating film having window; a recess formed on said silicon substrate within said window, said recess having a bottom face and a plurality of side faces, said bottom face having a (110) plane, and said side faces each having a (111) plane; a second gate insulating film formed on said silicon substrate within said window; a floating gate formed on said first gate insulating film, said floating gate covering fully said second gate insulating film; a third gate insulating film formed on said floating gate; and a control gate formed on said third gate insulating film.
Claim 6
Dependent Claim
132 words
A non-volatile semiconductor memory device comprising: a silicon substrate having a source region and a drain region each formed by a diffusion layer; a first gate insulating film formed on said silicon substrate, said first gate insulating film having window; a recess formed on said silicon substrate within said window, said recess having a bottom face and a plurality of side faces, said bottom face having a (110) plane, and said side faces each having a (111) plane; a second gate insulating film formed on said silicon substrate within said window; a floating gate formed on said first gate insulating film, said floating gate covering fully said second gate insulating film; a third gate insulating film formed on said floating gate; and a control gate formed on said third gate insulating film.
References Cited (Backward Citations)
JPH01207978A
Cited
US5210597A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |