US5254487A
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Method of manufacturing high and low voltage CMOS transistors on a single chip
Assignee: NEC Electronics Corp
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Filing: 1993-02-23
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Granted: 1993-10-19
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Expires: 2013-02-23
Abstract
Abstract A semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a single chip, is manufactured by a silicon gate CMOS process. In order to reduce the number of repetitions of photolithographic process, low voltage N channel transistor domains and high voltage P channel transistor domains are simultaneously implanted by B ion, and low voltage P channel transistor domains and high voltage N channel transistor domains are simultaneously implanted by P ion.
Inventors
- 👤 Akio Tamagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
184 words
Method of manufacturing a semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a same chip, by a silicon gate CMOS process, characterized in that the method comprises: process of forming N wells for low voltage P channel transistors and for high voltage P channel transistors in a P type Si substrate, by ion implantation and thermal diffusion, process of forming field oxide films for separating elements and gate oxide films, process of B ion implantation in high voltage N channel transistor domains for controlling threshold voltage, process of B ion implantation in high voltage P channel transistor domains for controlling threshold voltage, process of forming gate electrodes by generating a polysilicon film and by etching said polysilicon film selectively, process of simultaneous B ion implantation in low voltage N channel transistor domains for controlling threshold voltage and in high voltage P channel transistor domains for field intensity relaxation, process of simultaneous P ion implantation in low voltage P channel transistor domains for controlling threshold voltage and in high voltage N channel transistor domains for field intensity relaxation.
Claim 2
Dependent Claim
184 words
Method of manufacturing a semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a same chip, by a silicon gate CMOS process, characterized in that the method comprises: process of forming N wells for low voltage P channel transistors and for high voltage P channel transistors in a P type Si substrate, by ion implantation and thermal diffusion, process of forming field oxide films for separating elements and gate oxide films, process of B ion implantation in high voltage N channel transistor domains for controlling threshold voltage, process of B ion implantation in high voltage P channel transistor domains for controlling threshold voltage, process of forming gate electrodes by generating a polysilicon film and by etching said polysilicon film selectively, process of simultaneous B ion implantation in low voltage N channel transistor domains for controlling threshold voltage and in high voltage P channel transistor domains for field intensity relaxation, process of simultaneous P ion implantation in low voltage P channel transistor domains for controlling threshold voltage and in high voltage N channel transistor domains for field intensity relaxation.
Claim 3
Dependent Claim
27 words
Method of manufacturing a semiconductor device according to claim 1, in which said process of simultaneous B ion implantation precedes said process of simultaneous P ion implantation.
Claim 4
Dependent Claim
27 words
Method of manufacturing a semiconductor device according to claim 1, in which said process of simultaneous P ion implantation precedes said process of simultaneous B ion implantation.
Claim 5
Dependent Claim
186 words
Method of manufacturing a semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a same chip, by a silicon gate CMOS process, characterized in that the method comprises: process of forming N wells for low voltage P channel transistors and for high voltage P channel transistors in a P type Si substrate, by ion implantation and thermal diffusion, process of forming field oxide films for separating elements and gate oxide films, process of B ion implantation in high voltage N channel transistor domains for controlling threshold voltage, process of B ion implantation in high voltage P channel transistor domains for controlling threshold voltage, process of forming gate electrodes by generating a polysilicon film and by etching said polysilicon film selectively, process of simultaneous B ion implantation in low voltage N channel transistor source regions for controlling threshold voltage and in high voltage P channel transistor domains for field intensity relaxation, process of simultaneous P ion implantation in low voltage P channel transistor source regions for controlling threshold voltage and in high voltage N channel transistor domains for field intensity relaxation.
Claim 6
Dependent Claim
186 words
Method of manufacturing a semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a same chip, by a silicon gate CMOS process, characterized in that the method comprises: process of forming N wells for low voltage P channel transistors and for high voltage P channel transistors in a P type Si substrate, by ion implantation and thermal diffusion, process of forming field oxide films for separating elements and gate oxide films, process of B ion implantation in high voltage N channel transistor domains for controlling threshold voltage, process of B ion implantation in high voltage P channel transistor domains for controlling threshold voltage, process of forming gate electrodes by generating a polysilicon film and by etching said polysilicon film selectively, process of simultaneous B ion implantation in low voltage N channel transistor source regions for controlling threshold voltage and in high voltage P channel transistor domains for field intensity relaxation, process of simultaneous P ion implantation in low voltage P channel transistor source regions for controlling threshold voltage and in high voltage N channel transistor domains for field intensity relaxation.
Claim 7
Dependent Claim
27 words
Method of manufacturing a semiconductor device according to claim 4, in which said process of simultaneous B ion implantation precedes said process of simultaneous P ion implantation.
Claim 8
Dependent Claim
27 words
Method of manufacturing a semiconductor device according to claim 4, in which said process of simultaneous P ion implantation precedes said process of simultaneous B ion implantation.
Claim 9
Dependent Claim
184 words
Method of manufacturing a semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a same chip, by a silicon gate CMOS process, characterized in that the method comprises: process of forming P wells for low voltage N channel transistors and for high voltage N channel transistors in an N type Si substrate, by ion implantation and thermal diffusion, process of forming field oxide films for separating elements and gate oxide films, process of P ion implantation in high voltage P channel transistor domains for controlling threshold voltage, process of P ion implantation in high voltage N channel transistor domains for controlling threshold voltage, process of forming gate electrodes by generating a polysilicon film and by etching said polysilicon film selectively, process of simultaneous P ion implantation in low voltage P channel transistor domains for controlling threshold voltage and in high voltage N channel transistor domains for field intensity relaxation, process of simultaneous B ion implantation in low voltage N channel transistor domains for controlling threshold voltage and in high voltage P channel transistor domains for field intensity relaxation.
Claim 10
Dependent Claim
184 words
Method of manufacturing a semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a same chip, by a silicon gate CMOS process, characterized in that the method comprises: process of forming P wells for low voltage N channel transistors and for high voltage N channel transistors in an N type Si substrate, by ion implantation and thermal diffusion, process of forming field oxide films for separating elements and gate oxide films, process of P ion implantation in high voltage P channel transistor domains for controlling threshold voltage, process of P ion implantation in high voltage N channel transistor domains for controlling threshold voltage, process of forming gate electrodes by generating a polysilicon film and by etching said polysilicon film selectively, process of simultaneous P ion implantation in low voltage P channel transistor domains for controlling threshold voltage and in high voltage N channel transistor domains for field intensity relaxation, process of simultaneous B ion implantation in low voltage N channel transistor domains for controlling threshold voltage and in high voltage P channel transistor domains for field intensity relaxation.
Claim 11
Dependent Claim
27 words
Method of manufacturing a semiconductor device according to claim 7, in which said process of simultaneous P ion implantation precedes said process of simultaneous B ion implantation.
Claim 12
Dependent Claim
27 words
Method of manufacturing a semiconductor device according to claim 7, in which said process of simultaneous B ion implantation precedes said process of simultaneous P ion implantation.
Claim 13
Dependent Claim
186 words
Method of manufacturing a semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a same chip, by a silicon gate CMOS process, characterized in that the method comprises: process of forming P wells for low voltage N channel transistors and for high voltage N channel transistors in an N type Si substrate, by ion implantation and thermal diffusion, process of forming field oxide films for separating elements and gate oxide films, process of P ion implantation in high voltage P channel transistor domains for controlling threshold voltage, process of P ion implantation in high voltage N channel transistor domains for controlling threshold voltage, process of forming gate electrodes by generating a polysilicon film and by etching said polysilicon film selectively, process of simultaneous P ion implantation in low voltage P channel transistor source regions for controlling threshold voltage and in high voltage N channel transistor domains for field intensity relaxation, process of simultaneous B ion implantation in low voltage N channel transistor source regions for controlling threshold voltage and in high voltage P channel transistor domains for field intensity relaxation.
Claim 14
Dependent Claim
186 words
Method of manufacturing a semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a same chip, by a silicon gate CMOS process, characterized in that the method comprises: process of forming P wells for low voltage N channel transistors and for high voltage N channel transistors in an N type Si substrate, by ion implantation and thermal diffusion, process of forming field oxide films for separating elements and gate oxide films, process of P ion implantation in high voltage P channel transistor domains for controlling threshold voltage, process of P ion implantation in high voltage N channel transistor domains for controlling threshold voltage, process of forming gate electrodes by generating a polysilicon film and by etching said polysilicon film selectively, process of simultaneous P ion implantation in low voltage P channel transistor source regions for controlling threshold voltage and in high voltage N channel transistor domains for field intensity relaxation, process of simultaneous B ion implantation in low voltage N channel transistor source regions for controlling threshold voltage and in high voltage P channel transistor domains for field intensity relaxation.
Claim 15
Dependent Claim
27 words
Method of manufacturing a semiconductor device according to claim 10, in which said process of simultaneous P ion implantation precedes said process of simultaneous B ion implantation.
Claim 16
Dependent Claim
27 words
Method of manufacturing a semiconductor device according to claim 10, in which said process of simultaneous B ion implantation precedes said process of simultaneous P ion implantation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-10-18 | 1997-04-19 | 1997-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-18 | 2001-04-19 | 2001-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-18 | 2005-04-19 | 2005-10-19 | $7700.00 | Window Closed / Lapsed |