US5024960A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual LDD submicron CMOS process for making low and high voltage transistors with common gate
Assignee: Texas Instruments Inc
•
Filing: 1988-10-18
•
Granted: 1991-06-18
•
Expires: 2008-10-18
Abstract
Abstract The disclosure relates to a CMOS flow process for formation of high and low voltage transistors simultaneously in a single semiconductor chip. The low and high voltage transistors share the same gate oxide thickness and the same polysilicon gate level. This is accomplished without any additional masking steps and through the use of a separate lightly doped drain for the high voltage N-channel devices. The sources of the high voltage N-channel devices are fabricated using the more heavily concentrated LDD implant normally used for the low voltage transistors. This minimizes the source resistance of the high voltage transistor which results in higher performance through improved saturated transconductance. From a high voltage capability point of view, the flow permits the realization of a single level polysilicon single gate oxide thickness low/high voltage CMOS process.
Inventors
- 👤 Roger A. Haken
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:31
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0221; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8312; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
156 words
A method of making a CMOS integrated circuit comprising the steps of: providing a substrate; defining active regions in said substrate; forming a gate oxide of a selected thickness over said active regions; forming at least two gates over each of said active regions to define a source and drain region for a high voltage transistor and a source and drain region for a low voltage transistor; lightly doping each of said source and drain regions of said high voltage and low voltage transistors with an impurity of a selected type; doping said source regions of said high voltage and low voltage transistors and said drain region of said low voltage transistor of said active regions with additional impurity of said selected type; forming a sidewall oxide on each said gate; and further doping each of said source and drain regions of said high voltage and low voltage transistors with additional impurity of said selected type.
Claim 2
Independent Claim
156 words
A method of making a CMOS integrated circuit comprising the steps of: providing a substrate; defining active regions in said substrate; forming a gate oxide of a selected thickness over said active regions; forming at least two gates over each of said active regions to define a source and drain region for a high voltage transistor and a source and drain region for a low voltage transistor; lightly doping each of said source and drain regions of said high voltage and low voltage transistors with an impurity of a selected type; doping said source regions of said high voltage and low voltage transistors and said drain region of said low voltage transistor of said active regions with additional impurity of said selected type; forming a sidewall oxide on each said gate; and further doping each of said source and drain regions of said high voltage and low voltage transistors with additional impurity of said selected type.
Claim 3
Dependent Claim
42 words
The method of claim 1 and further comprising the step of masking the drain region of said high voltage transistor immediately subsequent to said lightly doping step to protect said drain region of said high voltage transistor from a subsequent doping step.
Claim 4
Dependent Claim
26 words
A method of making a CMOS integrated circuit as set forth in claim 1, wherein each of said high voltage and low voltage transistors is N-channel.
Claim 5
Dependent Claim
50 words
A method of making a CMOS integrated circuit as set forth in claim 3 and further including the step of forming additional P-channel transistors and wherein said gate oxide associated with said high voltage and low voltage transistors is contiguous with said gate oxide associated with said additional P-channel transistors.
Claim 6
Independent Claim
143 words
A method of making a CMOS integrated circuit comprising the steps of: (a) providing a substrate having a P-type region and an N-type region, (b) defining plural active regions in each of said P-type and said N-type regions, (c) forming a gate oxide over said active regions, (d) forming a polysilicon gate over each of said active regions to define a pair of source and drain regions in each active region, (e) lightly doping each of said source and drain regions with an N-type impurity, (f) doping both sources and one drain of each adjacent pair of active regions in each said P-type region with additional N-type impurity, (g) forming a side wall oxide on each said gate, (h) doping said P-type region only with additional N+ impurity, (i) doping said N-type region only with a P+ impurity, and (j) annealing said substrate.
Claim 7
Independent Claim
143 words
A method of making a CMOS integrated circuit comprising the steps of: (a) providing a substrate having a P-type region and an N-type region, (b) defining plural active regions in each of said P-type and said N-type regions, (c) forming a gate oxide over said active regions, (d) forming a polysilicon gate over each of said active regions to define a pair of source and drain regions in each active region, (e) lightly doping each of said source and drain regions with an N-type impurity, (f) doping both sources and one drain of each adjacent pair of active regions in each said P-type region with additional N-type impurity, (g) forming a side wall oxide on each said gate, (h) doping said P-type region only with additional N+ impurity, (i) doping said N-type region only with a P+ impurity, and (j) annealing said substrate.
Claim 8
Dependent Claim
17 words
A method as set forth in claim 5 wherein step (b) comprises formation of a field oxide.
Claim 9
Dependent Claim
27 words
A method as set forth in claim 6 wherein step (d) comprises formation of said gate over said active regions in said N-type and P-type regions simultaneously.
Claim 10
Dependent Claim
27 words
A method as set forth in claim 5 wherein step (d) comprises formation of said gate over said active regions in said N-type and P-type regions simultaneously.
References Cited (Backward Citations)
US4089712A
Cited
US4062699A
Cited
US4172260A
Cited
US4318216A
Cited
JPS57106166A
Cited
US4697332A
Cited
US4642878A
Cited
US4578128A
Cited
US4808548A
Cited
US4722909A
Cited
US4760033A
Cited
US4908327A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-17 | 1994-12-17 | 1995-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-17 | 1998-12-17 | 1999-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-17 | 2002-12-17 | 2003-06-18 | $7700.00 | Window Closed / Lapsed |