Method for forming a lateral MOS transistor having lightly doped drain formed along with other transistors in the same substrate

Claim 1

A method for forming a lateral MOS transistor having a lightly doped drain for increased breakdown voltage and for forming other transistors in the same substrate, said method comprising the steps of: forming a first gate for a lateral MOS transistor and a second gate for a DMOS transistor overlying and insulated from a semiconductor material; forming a first masking layer over said semiconductor material to mask a first area around said first gate and expose a second area around said second gate; implanting ions of a first conductivity type into said second area using said second gate and said first masking layer as a mask for forming a self-aligned body region of said first conductivity type for said DMOS transistor; removing said first masking layer to expose said first area around said first gate and expose said second area around said second gate; implanting ions of a second conductivity type into said first area and said second area, said first gate and said second gate acting as a mask to self-align implantation of said ions of said second conductivity type with said first gate and said second gate, said ions of said second conductivity type counter-doping said body region of said DMOS transistor and forming a lightly doped drain of said lateral transistor self-aligned with said first gate, said step of implanting said ions of said first conductivity type being adjusted to take into account said counter-doping from said implantation of said ions of said second conductivity type into said body region so that said body region has desired electrical characteristics; forming a second masking layer over a portion of said lightly doped drain to leave an exposed portion of said lightly doped drain; and implanting ions of said second conductivity type into said body region to form a source region of said DMOS transistor and into said exposed portion of said lightly doped drain to form a drain region of said lateral MOS transistor spaced from said first gate.

Claim 2

A method for forming a lateral MOS transistor having a lightly doped drain for increased breakdown voltage and for forming other transistors in the same substrate, said method comprising the steps of: forming a first gate for a lateral MOS transistor and a second gate for a DMOS transistor overlying and insulated from a semiconductor material; forming a first masking layer over said semiconductor material to mask a first area around said first gate and expose a second area around said second gate; implanting ions of a first conductivity type into said second area using said second gate and said first masking layer as a mask for forming a self-aligned body region of said first conductivity type for said DMOS transistor; removing said first masking layer to expose said first area around said first gate and expose said second area around said second gate; implanting ions of a second conductivity type into said first area and said second area, said first gate and said second gate acting as a mask to self-align implantation of said ions of said second conductivity type with said first gate and said second gate, said ions of said second conductivity type counter-doping said body region of said DMOS transistor and forming a lightly doped drain of said lateral transistor self-aligned with said first gate, said step of implanting said ions of said first conductivity type being adjusted to take into account said counter-doping from said implantation of said ions of said second conductivity type into said body region so that said body region has desired electrical characteristics; forming a second masking layer over a portion of said lightly doped drain to leave an exposed portion of said lightly doped drain; and implanting ions of said second conductivity type into said body region to form a source region of said DMOS transistor and into said exposed portion of said lightly doped drain to form a drain region of said lateral MOS transistor spaced from said first gate.