US5527722A
Expired / Lapsed
US
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Method of fabrication of a semiconductor device having high-and low-voltage MOS transistors
Assignee: Texas Instruments Inc
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Filing: 1995-05-08
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Granted: 1996-06-18
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Expires: 2015-05-08
Abstract
Abstract A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes source/drain regions (90a, 90b) having N- regions (90a 1 , 90b 1 ) that are self-aligned with a gate (78) and N+ regions (90a 2 , 90b 2 ) that are self-aligned with sidewall spacers (91) formed on sidewalls of the gate (78) to improve reliability under continuous high voltage operating conditions. The low voltage NMOS transistor includes source/drain regions (92a, 92b) that are self-aligned with sidewall spacers (92) to permit channel lengths to be scaled to less than 2 microns. The low-voltage PMOS transistor (82a) and high-voltage PMOS transistor (82b) include source/drain regions (116a-16d) that are self-aligned with sidewall spacer extension regions (110a) formed over sidewall spacers (91) permitting low-voltage PMOS transistor channel lengths to be scaled to less than 2 microns.
Inventors
- 👤 Louis N. Hutter
- 👤 Jeffrey P. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:21
CPC Classifications
H; H10; H10D; H10D88/00; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/8312; H10D84/8311
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
212 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a mask over said second gate and regions of said layer of P type semiconductor material adjacent said second gate, said mask exposing said first gate and regions of said layer of P type semiconductor material adjacent said first gate; doping said layer of P type semiconductor material with an N type impurity to form a first pair of N type regions in said layer of P type semiconductor material self-aligned with said first gate, said mask blocking said N type impurity from regions adjacent said second gate; removing said mask; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions, diffusing said third pair of N type regions to extend under said second gate.
Claim 2
Independent Claim
212 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a mask over said second gate and regions of said layer of P type semiconductor material adjacent said second gate, said mask exposing said first gate and regions of said layer of P type semiconductor material adjacent said first gate; doping said layer of P type semiconductor material with an N type impurity to form a first pair of N type regions in said layer of P type semiconductor material self-aligned with said first gate, said mask blocking said N type impurity from regions adjacent said second gate; removing said mask; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions, diffusing said third pair of N type regions to extend under said second gate.
Claim 3
Dependent Claim
94 words
The method of claim 1 further comprising the steps of: forming a fourth pair of N type regions self-aligned with said first pair of sidewall spacers and a fifth pair of N type regions self-aligned with said second pair of sidewall spacers, said fourth and filch pairs of N type regions extending farther into said layer of P type semiconductor material than said second and third pairs of N type regions, said second and third pairs of N type regions being more heavily doped than said fourth and fifth pairs of N type regions.
Claim 4
Dependent Claim
144 words
The method of claim 1 further comprising the steps of: forming an N well in said layer of P type semiconductor material; forming a third gate and a fourth gate over and insulated from said N well; forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate; forming an insulator layer over said N well, said insulator layer including a first pair of sidewall spacer extension regions formed over said third pair of sidewall spacers and a second pair of sidewall spacer extension regions formed over said fourth pair of sidewall spacers; forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions and a second pair of P type regions self-aligned with said second pair of sidewall spacer extension regions.
Claim 5
Dependent Claim
69 words
The method of claim 3 further comprising the steps of: connecting a first voltage source across said first and second pairs of N type regions and across said second pair of P type regions; connecting a second voltage source across said third pair of N type regions and across said first pair of P type regions, said first voltage source supplying a larger voltage than said second voltage source.
Claim 6
Dependent Claim
160 words
The method of claim 1 further comprising the steps of: forming an N well in said layer of P type semiconductor material; forming a third gate and a fourth gate over and insulated from said N well; forming a pair of N type regions in said N well self-aligned with said third gate; forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate; forming an insulator layer over said N well, said insulator layer including a first pair of sidewall spacer extension regions formed over said pair of third sidewall spacers and a second pair of sidewall spacer extension regions formed over said pair of fourth sidewall spacers; forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions and a second pair of P type regions self-aligned with said second pair of sidewall spacer extension regions.
Claim 7
Dependent Claim
69 words
The method of claim 5 further comprising the steps of: connecting a first voltage source across said first and second pairs of N type regions and across said second pair of P type regions; connecting a second voltage source across said third pair of N type regions and across said first pair of P type regions, said first voltage source supplying a larger voltage than said second voltage source.
Claim 8
Dependent Claim
111 words
The method of claim 1 further comprising the steps of: forming an N well in said layer of P type semiconductor material; forming a third gate and a fourth gate over and insulated from said N well; forming a pair of N type regions in said N well self-aligned with said third gate; forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate; forming a first pair of P type regions self-aligned with said third pair of sidewall spacers and a second pair of P type regions self-aligned with said fourth pair of sidewall spacers.
Claim 9
Dependent Claim
69 words
The method of claim 7 further comprising the steps of: connecting a first voltage source across said first and second pairs of N type regions and across said second pair of P type regions; connecting a second voltage source across said third pair of N type regions and across said first pair of P type regions, said first voltage source supplying a larger voltage than said second voltage source.
Claim 10
Dependent Claim
136 words
The method of claim 1 further comprising the steps of: forming an N well in said layer of P type semiconductor material; forming a third gate over and insulated from said N well and a polysilicon strip over and insulated from said layer of P type semiconductor material; forming a third pair of sidewall spacers on sidewalls of said third gate; forming an insulator layer over said layer of P type semiconductor material, said insulator layer including a first pair of sidewall spacer extension regions formed over said third pair of sidewall spacers; etching said insulator layer to expose opposite ends on said polysilicon strip; forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions; and forming layers of silicide on said exposed ends of said polysilicon strip.
Claim 11
Independent Claim
312 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a first pair of N type regions self-aligned with said first gate; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions; forming an N well in said layer of P type semiconductor material; forming a third gate and a fourth gate over and insulated from said N well; forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate; forming an insulator layer over said N well, said insulator layer including a first pair of sidewall spacer extension regions formed over said third pair of sidewall spacers and a second pair of sidewall spacer extension regions formed over said fourth pair of sidewall spacers; forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions and a second pair of P type regions self-aligned with said second pair of sidewall spacer extension regions; connecting a first voltage source across said first and second pairs of N type regions and across said second pair of P type regions; connecting a second voltage source across said third pair of N type regions and across said first pair of P type regions, said first voltage source supplying a larger voltage than said second voltage source.
Claim 12
Independent Claim
312 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a first pair of N type regions self-aligned with said first gate; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions; forming an N well in said layer of P type semiconductor material; forming a third gate and a fourth gate over and insulated from said N well; forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate; forming an insulator layer over said N well, said insulator layer including a first pair of sidewall spacer extension regions formed over said third pair of sidewall spacers and a second pair of sidewall spacer extension regions formed over said fourth pair of sidewall spacers; forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions and a second pair of P type regions self-aligned with said second pair of sidewall spacer extension regions; connecting a first voltage source across said first and second pairs of N type regions and across said second pair of P type regions; connecting a second voltage source across said third pair of N type regions and across said first pair of P type regions, said first voltage source supplying a larger voltage than said second voltage source.
Claim 13
Independent Claim
269 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a first pair of N type regions self-aligned with said first gate; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions; forming an N well in said layer of P type semiconductor material; forming a third gate and a fourth gate over and insulated from said N well; forming a pair of N type regions in said N well self-aligned with said third gate; forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate; forming an insulator layer over said N well, said insulator layer including a first pair of sidewall spacer extension regions formed over said pair of third sidewall spacers and a second pair of sidewall spacer extension regions formed over said pair of fourth sidewall spacers; forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions and a second pair of P type regions self-aligned with said second pair of sidewall spacer extension regions.
Claim 14
Independent Claim
269 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a first pair of N type regions self-aligned with said first gate; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions; forming an N well in said layer of P type semiconductor material; forming a third gate and a fourth gate over and insulated from said N well; forming a pair of N type regions in said N well self-aligned with said third gate; forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate; forming an insulator layer over said N well, said insulator layer including a first pair of sidewall spacer extension regions formed over said pair of third sidewall spacers and a second pair of sidewall spacer extension regions formed over said pair of fourth sidewall spacers; forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions and a second pair of P type regions self-aligned with said second pair of sidewall spacer extension regions.
Claim 15
Dependent Claim
69 words
The method of claim 11 further comprising the steps of: connecting a first voltage source across said first and second pairs of N type regions and across said second pair of P type regions; connecting a second voltage source across said third pair of N type regions and across said first pair of P type regions, said first voltage source supplying a larger voltage than said second voltage source.
Claim 16
Independent Claim
220 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a first pair of N type regions self-aligned with said first gate; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions; forming an N well in said layer of P type semiconductor material; forming a third gate and a fourth gate over and insulated from said N well; forming a pair of N type regions in said N well self-aligned with said third gate; forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate; forming a first pair of P type regions self-aligned with said third pair of sidewall spacers and a second pair of P type regions self-aligned with said fourth pair of sidewall spacers.
Claim 17
Independent Claim
220 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a first pair of N type regions self-aligned with said first gate; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions; forming an N well in said layer of P type semiconductor material; forming a third gate and a fourth gate over and insulated from said N well; forming a pair of N type regions in said N well self-aligned with said third gate; forming a third pair of sidewall spacers on sidewalls of said third gate and a fourth pair of sidewall spacers on sidewalls of said fourth gate; forming a first pair of P type regions self-aligned with said third pair of sidewall spacers and a second pair of P type regions self-aligned with said fourth pair of sidewall spacers.
Claim 18
Dependent Claim
68 words
The method of claim 13 further comprising the steps of: connecting a first voltage source across said first-and second pairs of N type regions and across said second pair of P type regions; connecting a second voltage source across said third pair of N type regions and across said first pair of P type regions, said first voltage source supplying a larger voltage than said second voltage source.
Claim 19
Independent Claim
245 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a first pair of N type regions self-aligned with said first gate; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions; forming an N well in said layer of P type semiconductor material; forming a third gate over and insulated from said N well and a polysilicon strip over and insulated from said layer of P type semiconductor material; forming a third pair of sidewall spacers on sidewalls of said third gate; forming an insulator layer over said layer of P type semiconductor material, said insulator layer including a first pair of sidewall spacer extension regions formed over said third pair of sidewall spacers; etching said insulator layer to expose opposite ends on said polysilicon strip; forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions; and forming layers of silicide on said exposed ends of said polysilicon strip.
Claim 20
Independent Claim
245 words
A method for forming a semiconductor device, comprising the steps of: forming first and second gates over and insulated from a layer of P type semiconductor material; forming a first pair of N type regions self-aligned with said first gate; forming a first pair of sidewall spacers on sidewalls of said first gate and a second pair of sidewall spacers on sidewalls of said second gate; forming a second pair of N type regions self-aligned with said first pair of sidewall spacers and a third pair of N type regions self-aligned with said second pair of sidewall spacers, said second and third pairs of N type regions being more heavily doped than said first pair of N type regions; forming an N well in said layer of P type semiconductor material; forming a third gate over and insulated from said N well and a polysilicon strip over and insulated from said layer of P type semiconductor material; forming a third pair of sidewall spacers on sidewalls of said third gate; forming an insulator layer over said layer of P type semiconductor material, said insulator layer including a first pair of sidewall spacer extension regions formed over said third pair of sidewall spacers; etching said insulator layer to expose opposite ends on said polysilicon strip; forming a first pair of P type regions self-aligned with said first pair of sidewall spacer extension regions; and forming layers of silicide on said exposed ends of said polysilicon strip.
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