Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof

Claim 1

A method of manufacturing a complementary insulated-gate field effect transistor integrated circuit comprising: a first step of forming a well of a first conductivity type on a primary surface of a silicon substrate; a second step of disposing an oxide layer on said primary surface and of disposing a nitride layer on said oxide layer; a third step of applying a mask to said nitride layer and of etching said nitride layer excepting a region to be used to form a transistor; a fourth step of respectively implanting ions in an area to be used to form a p-channel transistor and an area to be used to form an n-channel transistor, for forming field oxide isolation regions; a fifth step of applying a mask to the area to be used to form the p-channel transistor and of removing the nitride layer and the oxide layer on the region to be used to form the n-channel transistor through an etching; a sixth step of growing an oxide layer on the region to be used to form the n-channel transistor; a seventh step of applying a mask to the region to be used to form the n-channel transistor and of removing the nitride layer and the oxide layer on the region to be used to form the p-channel transistor through an etching; an eighth step of growing an oxide layer on the regions to be used to form the p-channel and n-channel transistors; a ninth step of depositing a polycrystalline silicon layer on said primary surface; a tenth step of applying a mask to a region of said polycrystalline silicon layer to be used to form the p-channel transistor, of implanting a first impurity substance in a region of said polycrystalline silicon layer not masked, and of activating the first impurity substance; an eleventh step of removing said mask and of implanting a second impurity substance in the whole polycrystalline silicon layer; a twelfth step of forming on a surface of said polycrystalline silicon layer a mask having substantially the same strip width in association with a gate electrode of the transistor; a thirteenth step of effecting a plasma etching to remove portions of said polycrystalline silicon layer not covered with said mask; and a fourteenth step of removing said mask, of diffusing a third impurity substance having a high diffusion constant in the region of said polycrystalline silicon layer to be used to form the p-channel transistor, and of diffusing a fourth impurity substance having a low diffusion constant in the region of said polycrystalline silicon layer to be used to form the n-channel transistor, thereby forming source and drain regions of the p-channel and n-channel transistors.

Claim 2

A method of manufacturing a complementary insulated-gate field effect transistor integrated circuit comprising: a first step of forming a well of a first conductivity type on a primary surface of a silicon substrate; a second step of disposing an oxide layer on said primary surface and of disposing a nitride layer on said oxide layer; a third step of applying a mask to said nitride layer and of etching said nitride layer excepting a region to be used to form a transistor; a fourth step of respectively implanting ions in an area to be used to form a p-channel transistor and an area to be used to form an n-channel transistor, for forming field oxide isolation regions; a fifth step of applying a mask to the area to be used to form the p-channel transistor and of removing the nitride layer and the oxide layer on the region to be used to form the n-channel transistor through an etching; a sixth step of growing an oxide layer on the region to be used to form the n-channel transistor; a seventh step of applying a mask to the region to be used to form the n-channel transistor and of removing the nitride layer and the oxide layer on the region to be used to form the p-channel transistor through an etching; an eighth step of growing an oxide layer on the regions to be used to form the p-channel and n-channel transistors; a ninth step of depositing a polycrystalline silicon layer on said primary surface; a tenth step of applying a mask to a region of said polycrystalline silicon layer to be used to form the p-channel transistor, of implanting a first impurity substance in a region of said polycrystalline silicon layer not masked, and of activating the first impurity substance; an eleventh step of removing said mask and of implanting a second impurity substance in the whole polycrystalline silicon layer; a twelfth step of forming on a surface of said polycrystalline silicon layer a mask having substantially the same strip width in association with a gate electrode of the transistor; a thirteenth step of effecting a plasma etching to remove portions of said polycrystalline silicon layer not covered with said mask; and a fourteenth step of removing said mask, of diffusing a third impurity substance having a high diffusion constant in the region of said polycrystalline silicon layer to be used to form the p-channel transistor, and of diffusing a fourth impurity substance having a low diffusion constant in the region of said polycrystalline silicon layer to be used to form the n-channel transistor, thereby forming source and drain regions of the p-channel and n-channel transistors.