US4295266A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing bulk CMOS integrated circuits
Assignee: Intersil Corp
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Filing: 1980-06-30
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Granted: 1981-10-20
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Expires: 2000-06-30
Abstract
Abstract The method presented may be utilized in manufacturing CMOS integrated circuits either in an isoplanar or in a LOCOS process. The method entails the simultaneous formation of the well region with the oxide isolation regions by a drive-in diffusion which is conducted in a dry oxygen ambient. The utilization of the process insures that compounds of silicon, nitrogen and oxygen will not be present in the bulk silicon where they can effect the quality of gate oxides which are subsequently formed.
Inventors
- 👤 Sheng T. Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:33
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/13; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/20; H10P76/40; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0123; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/92
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
173 words
An improved method for manufacturing a complementary symmetry metal oxide semiconductor integrated circuit comprising the steps of: (a) forming an oxide layer on the surface of a semiconductor substrate of a first conductivity type; (b) forming a silicon nitride layer on the surface of said oxide layer; (c) defining said silicon nitride layer to cover areas where transistors will be formed in said substrate; and (d) applying a photoresist layer over said defined silicon nitride layer; wherein the improvement comprises the steps of: (a) defining openings in said photoresist layer over areas where well regions of opposite conductivity type to said substrate will be formed; (b) implanting ions through said defined silicon nitride layer, through the underlying portions of said oxide layer and into said substrate; (c) removing said photoresist layer; (d) simultaneously driving said implanted ions into said substrate while growing a thermal oxide by heating said substrate in a dry oxygen ambient; (e) removing the silicon nitride layer and any underlying silicon dioxide portions; and (f) growing a gate oxide layer.
Claim 2
Dependent Claim
173 words
An improved method for manufacturing a complementary symmetry metal oxide semiconductor integrated circuit comprising the steps of: (a) forming an oxide layer on the surface of a semiconductor substrate of a first conductivity type; (b) forming a silicon nitride layer on the surface of said oxide layer; (c) defining said silicon nitride layer to cover areas where transistors will be formed in said substrate; and (d) applying a photoresist layer over said defined silicon nitride layer; wherein the improvement comprises the steps of: (a) defining openings in said photoresist layer over areas where well regions of opposite conductivity type to said substrate will be formed; (b) implanting ions through said defined silicon nitride layer, through the underlying portions of said oxide layer and into said substrate; (c) removing said photoresist layer; (d) simultaneously driving said implanted ions into said substrate while growing a thermal oxide by heating said substrate in a dry oxygen ambient; (e) removing the silicon nitride layer and any underlying silicon dioxide portions; and (f) growing a gate oxide layer.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein said semiconductor substrate is comprised of silicon.
Claim 4
Dependent Claim
15 words
The method of claim 3 wherein said oxide layer comprises a layer of silicon dioxide.
Claim 5
Dependent Claim
15 words
The method of claim 3 wherein said silicon substrate is comprised of N type silicon.
Claim 6
Dependent Claim
35 words
The method of claim 4 further comprising the step of removing the portions of said oxide layer which do not underlie said defined silicon nitride layer prior to said step of applying a photoresist layer.
Claim 7
Dependent Claim
30 words
The method of claim 5 further comprising the step of removing portions of said semiconductor substrate which are exposed following the removal of said exposed portions of said oxide layer.
Claim 8
Dependent Claim
21 words
The method of claim 6 further comprising the step of forming an oxide layer on said exposed portions of said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-19 | 1985-04-20 | 1985-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-19 | 1989-04-20 | 1989-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-19 | 1993-04-20 | 1993-10-20 | $7700.00 | Window Closed / Lapsed |