N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel

Claim 1

A method of fabricating complimentary P-channel and N-channel insulated gate field effect transistors in a P-conductivity type substrate which comprises the steps of: (a) forming a first masking layer over said substrate with a first opening to define the surface of said P-channel transistor, and a second and third opening at the surface areas at which a source and drain of said N-channel transistor is to be formed; (b) simultaneously introducing impurities into said substrate through said first, second and third openings to form a deep N-conductivity type well region in which said P-channel transistor is to be formed and to form deep N-conductivity type well regions in which respectively said source and drain of said N-channel transistor is to be formed; (c) removing said first masking layer; (d) growing a gate oxide layer over the substrate region at which said N-channel transistor is to be formed; (e) forming a conductive gate over a central portion of said N-channel transistor region; and (f) implanating N-type impurities through said gate oxide on either side of said gate into said source and drain areas to form said source and drain of said N-type transistor which are substantially more heavily doped and shallower than said corresponding underlying N-type wells.

Claim 2

A method of fabricating complimentary P-channel and N-channel insulated gate field effect transistors in a P-conductivity type substrate which comprises the steps of: (a) forming a first masking layer over said substrate with a first opening to define the surface of said P-channel transistor, and a second and third opening at the surface areas at which a source and drain of said N-channel transistor is to be formed; (b) simultaneously introducing impurities into said substrate through said first, second and third openings to form a deep N-conductivity type well region in which said P-channel transistor is to be formed and to form deep N-conductivity type well regions in which respectively said source and drain of said N-channel transistor is to be formed; (c) removing said first masking layer; (d) growing a gate oxide layer over the substrate region at which said N-channel transistor is to be formed; (e) forming a conductive gate over a central portion of said N-channel transistor region; and (f) implanating N-type impurities through said gate oxide on either side of said gate into said source and drain areas to form said source and drain of said N-type transistor which are substantially more heavily doped and shallower than said corresponding underlying N-type wells.