Patent US7494873B2 successfully refreshed from Google Patents.
US7494873B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory utilizing oxide-nitride nanolaminates
Assignee: Micron Technology Inc
•
Filing: 2006-07-25
•
Granted: 2009-02-24
•
Expires: 2026-07-25
Abstract
Abstract Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.
Inventors
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5671; H; H10; H10B; H10B43/00; H10B43/30; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/69; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
349 words
A method for forming a memory array, comprising: forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, wherein along columns of the pillars adjacent pillars include a first transistor on one side of a trench and a second transistor on the opposite side of the trench, and wherein forming the gate insulator includes atomic layer depositing a storage layer within silicon dioxide as part of a nanolaminate; forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; forming a number of word lines coupled to the gate of each transistor along columns of the memory array; forming a number of sourcelines in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that the first transistor and the second transistor share a common sourceline; wherein the number of vertical pillars can be programmed in a first direction to have a charge trapped in the gate insulator adjacent to the first source/drain region by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a gate by a wordline address, and wherein the number of vertical pillars are configured to be read in a second direction opposite from the first direction; and coupling circuitry to the first transistor and to the second transistor to compare electrical characteristics in the channel region of the first transistor with electrical characteristics of the channel in the second transistor wherein the second transistor functions as a reference transistor.
Claim 2
Independent Claim
349 words
A method for forming a memory array, comprising: forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator in the trenches along rows of pillars, wherein along columns of the pillars adjacent pillars include a first transistor on one side of a trench and a second transistor on the opposite side of the trench, and wherein forming the gate insulator includes atomic layer depositing a storage layer within silicon dioxide as part of a nanolaminate; forming a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; forming a number of word lines coupled to the gate of each transistor along columns of the memory array; forming a number of sourcelines in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couple to the sourceline in a shared trench such that the first transistor and the second transistor share a common sourceline; wherein the number of vertical pillars can be programmed in a first direction to have a charge trapped in the gate insulator adjacent to the first source/drain region by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a gate by a wordline address, and wherein the number of vertical pillars are configured to be read in a second direction opposite from the first direction; and coupling circuitry to the first transistor and to the second transistor to compare electrical characteristics in the channel region of the first transistor with electrical characteristics of the channel in the second transistor wherein the second transistor functions as a reference transistor.
Claim 3
Dependent Claim
34 words
The method of claim 1 , wherein forming a number of sourcelines in a bottom of the trenches between rows of the pillars includes implanting a doped region in the bottom of the trench.
Claim 4
Dependent Claim
38 words
The method of claim 1 , wherein forming a gate insulator above the channel region in the trenches along rows of pillars includes forming a gate insulator having a thickness less than or equal to 10 nanometers (nm).
Claim 5
Dependent Claim
19 words
The method of claim 1 , wherein atomic layer depositing a storage layer includes atomic layer depositing silicon nitride.
Claim 6
Dependent Claim
19 words
The method of claim 1 , wherein atomic layer depositing a storage layer includes atomic layer depositing aluminum nitride.
Claim 7
Dependent Claim
19 words
The method of claim 1 , wherein atomic layer depositing a storage layer includes atomic layer depositing gallium nitride.
Claim 8
Dependent Claim
20 words
The method of claim 1 , wherein atomic layer depositing a storage layer includes atomic layer depositing gallium aluminum nitride.
Claim 9
Dependent Claim
20 words
The method of claim 1 , wherein atomic layer depositing a storage layer includes atomic layer depositing tantalum aluminum nitride.
Claim 10
Dependent Claim
20 words
The method of claim 1 , wherein atomic layer depositing a storage layer includes atomic layer depositing titanium silicon nitride.
Claim 11
Dependent Claim
20 words
The method of claim 1 , wherein atomic layer depositing a storage layer includes atomic layer depositing titanium aluminum nitride.
Claim 12
Dependent Claim
20 words
The method of claim 1 , wherein atomic layer depositing a storage layer includes atomic layer depositing tungsten aluminum nitride.
Claim 13
Independent Claim
184 words
A method of forming a memory array, comprising: forming a number of vertical pillars in a semiconductor substrate, the vertical pillars separated by trenches; forming a pair of vertical transistors on opposing sides of the trench, wherein forming a transistor includes: forming a first source/drain region adjacent to a bottom of a pillar; forming a second source/drain region adjacent to a top of the pillar; forming a nanolaminate insulator over a channel region on a wall of the pillar between the first source/drain region and the second source/drain region, the nanolaminate insulator including a storage layer formed by atomic layer deposition techniques; forming a gate over the nanolaminate insulator layer; coupling circuitry to the pair of vertical transistors wherein the circuitry is operable to program a first transistor in a first direction, and read the first transistor in a second direction opposite from the first direction and wherein the pair of vertical transistors are configured to compare electrical characteristics in a channel region of the first transistor with electrical characteristics of a channel in a second transistor of the pair as a reference transistor.
Claim 14
Independent Claim
184 words
A method of forming a memory array, comprising: forming a number of vertical pillars in a semiconductor substrate, the vertical pillars separated by trenches; forming a pair of vertical transistors on opposing sides of the trench, wherein forming a transistor includes: forming a first source/drain region adjacent to a bottom of a pillar; forming a second source/drain region adjacent to a top of the pillar; forming a nanolaminate insulator over a channel region on a wall of the pillar between the first source/drain region and the second source/drain region, the nanolaminate insulator including a storage layer formed by atomic layer deposition techniques; forming a gate over the nanolaminate insulator layer; coupling circuitry to the pair of vertical transistors wherein the circuitry is operable to program a first transistor in a first direction, and read the first transistor in a second direction opposite from the first direction and wherein the pair of vertical transistors are configured to compare electrical characteristics in a channel region of the first transistor with electrical characteristics of a channel in a second transistor of the pair as a reference transistor.
Claim 15
Dependent Claim
14 words
The method of claim 12 , wherein comparing electrical characteristics includes comparing source/drain current.
Claim 16
Dependent Claim
26 words
The method of claim 12 , wherein forming a nanolaminate insulator includes forming a storage layer having a thickness less than or equal to 10 nanometers.
Claim 17
Dependent Claim
24 words
The method of claim 14 , wherein forming a nanolaminate insulator includes forming a storage layer having a thickness approximately equal to 4 nanometers.
Claim 18
Independent Claim
197 words
A method of forming a memory array, comprising: forming a number of vertical pillars in a semiconductor substrate, the vertical pillars separated by trenches; forming a pair of vertical transistors on opposing sides of the trench, wherein forming a transistor includes: forming a first source/drain region adjacent to a bottom of a pillar; forming a second source/drain region adjacent to a top of the pillar; forming a nanolaminate insulator over a channel region on a wall of the pillar between the first source/drain region and the second source/drain region, the nanolaminate insulator including a storage layer formed by atomic layer deposition techniques; forming a gate within the trench that serves as a common gate between transistors on the opposing sides of the trench; coupling circuitry to the pair of vertical transistors wherein the circuitry is operable to program a first transistor in a first direction, and read the first transistor in a second direction opposite from the first direction and wherein the pair of vertical transistors are configured to compare electrical characteristics in a channel region of the first transistor with electrical characteristics of a channel in a second transistor of the pair as a reference transistor.
Claim 19
Independent Claim
197 words
A method of forming a memory array, comprising: forming a number of vertical pillars in a semiconductor substrate, the vertical pillars separated by trenches; forming a pair of vertical transistors on opposing sides of the trench, wherein forming a transistor includes: forming a first source/drain region adjacent to a bottom of a pillar; forming a second source/drain region adjacent to a top of the pillar; forming a nanolaminate insulator over a channel region on a wall of the pillar between the first source/drain region and the second source/drain region, the nanolaminate insulator including a storage layer formed by atomic layer deposition techniques; forming a gate within the trench that serves as a common gate between transistors on the opposing sides of the trench; coupling circuitry to the pair of vertical transistors wherein the circuitry is operable to program a first transistor in a first direction, and read the first transistor in a second direction opposite from the first direction and wherein the pair of vertical transistors are configured to compare electrical characteristics in a channel region of the first transistor with electrical characteristics of a channel in a second transistor of the pair as a reference transistor.
Claim 20
Dependent Claim
30 words
The method of claim 16 , further including forming a sourceline in a base of the trench wherein the sourceline is common to transistors on opposing sides of the trench.
Claim 21
Dependent Claim
31 words
The method of claim 17 , wherein forming a sourceline in the base of the trench includes implanting a dopant into a base of the trench to form a conductive sourceline.
Claim 22
Dependent Claim
14 words
The method of claim 16 , wherein the storage layer includes a nitride layer.
Claim 23
Dependent Claim
38 words
The method of claim 16 , wherein forming a storage layer by atomic layer deposition techniques includes forming a storage layer with an electron affinity less than 4.1 eV providing a positive conduction band offset with silicon oxide.
References Cited (Backward Citations)
US3665423A
Cited
US3877054A
Cited
US3964085A
Cited
US4217601A
Cited
US4507673A
Cited
US4939559A
Cited
US4661833A
Cited
US5017977A
Cited
US5016215A
Cited
US5021999A
Cited
US6630381B1
Cited
US5293560A
Cited
US5111430A
Cited
US5027171A
Cited
JPH03222367A
Cited
US6110529A
Cited
US5253196A
Cited
US5677867A
Cited
US5449941A
Cited
US5303182A
Cited
US5274249A
Cited
US5388069A
Cited
US5317535A
Cited
US5409859A
Cited
US5508544A
Cited
JPH06224431A
Cited
US5438544A
Cited
JPH06302828A
Cited
US6521950B1
Cited
US5493140A
Cited
US5298447A
Cited
US5467306A
Cited
US5430670A
Cited
US5424993A
Cited
US5434815A
Cited
US5508543A
Cited
US5485422A
Cited
US5602777A
Cited
US5627781A
Cited
US5477485A
Cited
US6714455B2
Cited
US6353554B1
Cited
JPH08255878A
Cited
US5530581A
Cited
US5670790A
Cited
US5714766A
Cited
US5795808A
Cited
US5768192A
Cited
US5912488A
Cited
US5698022A
Cited
US5916365A
Cited
US6166401A
Cited
US5754477A
Cited
US5959896A
Cited
US5852306A
Cited
US5989958A
Cited
US5801401A
Cited
US6115281A
Cited
US6238976B1
Cited
US5973356A
Cited
US6150687A
Cited
US5936274A
Cited
US6072209A
Cited
US6143636A
Cited
US6013553A
Cited
US6031263A
Cited
US5886368A
Cited
US6249020B1
Cited
US6566699B2
Cited
US6552387B1
Cited
US6011725A
Cited
US6020024A
Cited
US5828605A
Cited
US6313518B1
Cited
US6194228B1
Cited
US6351411B2
Cited
US6140181A
Cited
US6545314B2
Cited
US6246606B1
Cited
US6232643B1
Cited
US5943262A
Cited
US5991225A
Cited
US6153468A
Cited
US6124729A
Cited
US6294813B1
Cited
US6225168B1
Cited
US6027961A
Cited
US20020003252A1
Cited
US6005790A
Cited
US6255683B1
Cited
US6380579B1
Cited
US6171900B1
Cited
US6160739A
Cited
US6504755B1
Cited
US6580118B2
Cited
US6297539B1
Cited
US6521958B1
Cited
US20020027264A1
Cited
US6049479A
Cited
US6203613B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2012-02-24 | 2012-08-25 | 2013-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2016-02-24 | 2016-08-25 | 2017-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2020-02-24 | 2020-08-25 | 2021-02-24 | $7700.00 | Window Closed / Lapsed |