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US7193893B2
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US
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Write once read only memory employing floating gates
Assignee: Micron Technology Inc
•
Filing: 2002-06-21
•
Granted: 2007-03-20
•
Expires: 2022-06-21
Abstract
Abstract Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate transistor has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The floating gate transistor can be programmed by trapping charge on the floating gate.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:42
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
123 words
A write once read only memory cell, comprising: a floating gate transistor, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a plug coupled to the first source/drain region, wherein the plug couples the first source/drain region to an array plate; a transmission line coupled to the second source/drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate such that the programmed floating gate transistor operates at reduced drain source current.
Claim 2
Dependent Claim
123 words
A write once read only memory cell, comprising: a floating gate transistor, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a plug coupled to the first source/drain region, wherein the plug couples the first source/drain region to an array plate; a transmission line coupled to the second source/drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate such that the programmed floating gate transistor operates at reduced drain source current.
Claim 3
Dependent Claim
39 words
The write once read only memory cell of claim 1 , wherein the first source/drain region of the floating gate transistor includes a source region and the second source/drain region of the floating gate transistor includes a drain region.
Claim 4
Dependent Claim
19 words
The write once read only memory cell of claim 1 , wherein the transmission line includes a bit line.
Claim 5
Dependent Claim
24 words
The write once read only memory cell of claim 1 , wherein the charge trapped in the floating gate includes a trapped electron charge.
Claim 6
Dependent Claim
32 words
The write once read only memory cell of claim 1 , wherein the write once read only memory (WOROM) cell is formed in a modified dynamic random access memory (DRAM) fabrication process.
Claim 7
Dependent Claim
24 words
The write once read only memory cell of claim 1 , wherein the gate insulator has a thickness of at least 10 nanometers (nm).
Claim 8
Dependent Claim
112 words
A write once read only memory cell, comprising: a floating gate transistor formed according to a modified DRAM fabrication process, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a wordline coupled to the control gate; an array plate coupled to the source region; a bit line coupled to the drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate.
Claim 9
Dependent Claim
112 words
A write once read only memory cell, comprising: a floating gate transistor formed according to a modified DRAM fabrication process, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a wordline coupled to the control gate; an array plate coupled to the source region; a bit line coupled to the drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate.
Claim 10
Dependent Claim
24 words
The write once read only memory cell of claim 7 , wherein the gate insulator has a thickness of at least 10 nanometers (nm).
Claim 11
Dependent Claim
192 words
A memory array, comprising: a number of write once read only floating gate memory cells, wherein each write once read only floating gate memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a number of bit lines coupled to the second source/drain region of each write once read only floating gate memory cell along rows of the memory array; a number of word lines coupled to the control gate of each write once read only floating gate memory cell along columns of the memory array; an array plate, wherein the first source/drain region of each write once read only floating gate memory cell is coupled to the array plate by a conductive plug; and wherein at least one of write once read only floating gate memory cells is a programmed floating gate transistor having a charge trapped in the floating gate such that the programmed floating gate transistor operates at reduced drain source current.
Claim 12
Dependent Claim
192 words
A memory array, comprising: a number of write once read only floating gate memory cells, wherein each write once read only floating gate memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a number of bit lines coupled to the second source/drain region of each write once read only floating gate memory cell along rows of the memory array; a number of word lines coupled to the control gate of each write once read only floating gate memory cell along columns of the memory array; an array plate, wherein the first source/drain region of each write once read only floating gate memory cell is coupled to the array plate by a conductive plug; and wherein at least one of write once read only floating gate memory cells is a programmed floating gate transistor having a charge trapped in the floating gate such that the programmed floating gate transistor operates at reduced drain source current.
Claim 13
Dependent Claim
22 words
The memory array of claim 9 , wherein the charge trapped in the floating gate includes a charge of approximately 100 electrons.
Claim 14
Dependent Claim
35 words
The memory array of claim 9 , wherein the first source/drain region of the floating gate cell includes a source region and the second source/drain region of the floating gate cell includes a drain region.
Claim 15
Dependent Claim
30 words
The memory array of claim 9 , wherein the number of write once read only memory (WOROM) cell are formed in a modified dynamic random access memory (DRAM) fabrication process.
Claim 16
Dependent Claim
30 words
The memory array of claim 9 , wherein the gate insulator of each write once read only floating gate memory cell has a thickness of at least 10 nanometers (nm).
Claim 17
Dependent Claim
219 words
A memory device, comprising: a memory array, wherein the memory array includes a number of write once read only floating gate memory cells, wherein each write once read only floating gate memory cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a number of bitlines coupled to the drain region of each write once read only floating gate memory cell along rows of the memory array; a number of wordlines coupled to the control gate of each write once read only floating gate memory cell along columns of the memory array; an array plate, wherein the source region of each write once read only floating gate memory cell is coupled to the array plate by a conductive plug; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; a sense amplifier coupled to the number of bitlines; and wherein at least one of write once read only floating gate memory cells is a programmed flash cell having a charge trapped in the floating gate such that the programmed flash cell operates at reduced drain/source current.
Claim 18
Dependent Claim
219 words
A memory device, comprising: a memory array, wherein the memory array includes a number of write once read only floating gate memory cells, wherein each write once read only floating gate memory cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a number of bitlines coupled to the drain region of each write once read only floating gate memory cell along rows of the memory array; a number of wordlines coupled to the control gate of each write once read only floating gate memory cell along columns of the memory array; an array plate, wherein the source region of each write once read only floating gate memory cell is coupled to the array plate by a conductive plug; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; a sense amplifier coupled to the number of bitlines; and wherein at least one of write once read only floating gate memory cells is a programmed flash cell having a charge trapped in the floating gate such that the programmed flash cell operates at reduced drain/source current.
Claim 19
Dependent Claim
22 words
The memory device of claim 14 , wherein the charge trapped in the floating gate includes a charge of approximately 100 electrons.
Claim 20
Dependent Claim
30 words
The memory device of claim 14 , wherein the number of write once read only memory (WOROM) cell is formed in a modified dynamic random access memory (DRAM) fabrication process.
Claim 21
Dependent Claim
30 words
The memory device of claim 14 , wherein the gate insulator of each write once read only floating gate memory cell has a thickness of at least 10 nanometers (nm).
Claim 22
Dependent Claim
33 words
The memory device of claim 14 , wherein the wordline address decoder and the bitline address decoder each include conventionally fabricated transistors having thin gate insulators formed of silicon dioxide (SiO 2 ).
Claim 23
Dependent Claim
26 words
The memory device of claim 14 , wherein the sense amplifier includes conventionally fabricated transistors having thin gate insulators formed of silicon dioxide (SiO 2 ).
Claim 24
Dependent Claim
234 words
An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes; a memory array, wherein the memory array includes a number of write once read only floating gate memory cells, wherein each write once read only floating gate memory cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a number of bitlines coupled to the drain region of each write once read only floating gate memory cell along rows of the memory array; a number of wordlines coupled to the control gate of each write once read only floating gate memory cell along columns of the memory array; an array plate, wherein the source region of each write once read only floating gate memory cell is coupled to the array plate by a conductive plug; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; a sense amplifier coupled to the number of bitlines; and wherein at least one of write once read only floating gate memory cells is a programmed flash cell having a charge trapped in the floating gate such that the programmed flash cell operates at reduced drain/source current.
Claim 25
Dependent Claim
234 words
An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes; a memory array, wherein the memory array includes a number of write once read only floating gate memory cells, wherein each write once read only floating gate memory cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a number of bitlines coupled to the drain region of each write once read only floating gate memory cell along rows of the memory array; a number of wordlines coupled to the control gate of each write once read only floating gate memory cell along columns of the memory array; an array plate, wherein the source region of each write once read only floating gate memory cell is coupled to the array plate by a conductive plug; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; a sense amplifier coupled to the number of bitlines; and wherein at least one of write once read only floating gate memory cells is a programmed flash cell having a charge trapped in the floating gate such that the programmed flash cell operates at reduced drain/source current.
Claim 26
Dependent Claim
22 words
The electronic system of claim 20 , wherein the charge trapped in the floating gate includes a charge of approximately 100 electrons.
Claim 27
Dependent Claim
53 words
The electronic system of claim 20 , wherein, in a read operation, the array plate is coupled to a ground potential, the drain region of an addressed write once read only floating gate memory cell is precharged to a fractional voltage of VDD, and the memory cell is selected by a wordline address.
Claim 28
Dependent Claim
50 words
The electronic system of claim 20 , wherein, in a write operation, the array plate is biased to a voltage higher than VDD, the drain region of an addressed write once read only memory cell is couple to a ground, and the memory cell is selected by a wordline address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-03-19 | 2010-09-18 | 2011-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-03-19 | 2014-09-18 | 2015-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-03-19 | 2018-09-18 | 2019-03-20 | $7700.00 | Window Closed / Lapsed |