Patent US6499111B2 successfully refreshed from Google Patents.
US6499111B2
Expired / Lapsed
US
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Apparatus for adjusting delay of a clock signal relative to a data signal
Assignee: Round Rock Research LLC
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Filing: 2001-07-16
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Granted: 2002-12-24
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Expires: 2021-07-16
Abstract
Abstract A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting circuit accepts a plurality of control signals each arranged to control passgates arranged in columns, with one column being controlled by a respective one of the control signals. A clock signal passes in parallel manner through a variety of delay gates, and each delay gate is coupled in series with one of the passgates. By selecting a path through desired passgates, one delay path is selected and the delay time added to the clock signal. This delayed clock signal is used to control the data passing circuit, which controls when data is output to the output terminals relative to the original clock signal. The control signals are created by selectively coupling or decoupling the control signals from a static voltage, and fuses or antifuses can be used to facilitate this coupling or decoupling.
Inventors
- 👤 Patrick J. Mullarkey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:41
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F2205/00; G06F2205/10; G06F2205/104
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
221 words
A synchronous memory device comprising: a data bus having a plurality of data bus terminals; an address decoder; a control logic circuit structured to generate control signals responsive to memory commands; a memory-cell array coupled to the address decoder and the control logic circuit; a data path coupled between the memory-cell array and the data bus, the data path circuit including for each of the data bus terminals a data delay circuit, the data delay circuit comprising: an adjustable time delay circuit having at least one delay control input, each delay control input coupled to receive a respective delay control signal, the time delay circuit coupled to receive a clock signal and to generate a delayed clock signal, the time between when the clock signal changes state and when the delayed clock signal changes state being determined by the at least one delay control signal applied to respective delay control inputs, and a data passing circuit having a data input terminal and a data output terminal, the data passing circuit receiving the delayed clock signal and being structured to pass a data signal from the data input terminal to a data output terminal responsive to the delayed clock signal changing state, the data input terminal and the data output terminal coupled between the memory-cell array and a respective data bus terminal.
Claim 2
Dependent Claim
221 words
A synchronous memory device comprising: a data bus having a plurality of data bus terminals; an address decoder; a control logic circuit structured to generate control signals responsive to memory commands; a memory-cell array coupled to the address decoder and the control logic circuit; a data path coupled between the memory-cell array and the data bus, the data path circuit including for each of the data bus terminals a data delay circuit, the data delay circuit comprising: an adjustable time delay circuit having at least one delay control input, each delay control input coupled to receive a respective delay control signal, the time delay circuit coupled to receive a clock signal and to generate a delayed clock signal, the time between when the clock signal changes state and when the delayed clock signal changes state being determined by the at least one delay control signal applied to respective delay control inputs, and a data passing circuit having a data input terminal and a data output terminal, the data passing circuit receiving the delayed clock signal and being structured to pass a data signal from the data input terminal to a data output terminal responsive to the delayed clock signal changing state, the data input terminal and the data output terminal coupled between the memory-cell array and a respective data bus terminal.
Claim 3
Dependent Claim
44 words
The synchronous memory device of claim 1 wherein the data input terminal of the data passing circuit is coupled to the memory-cell array, and the data output terminal of the data passing circuit is coupled to a respective one of the data bus terminals.
Claim 4
Dependent Claim
34 words
The synchronous memory device of claim 1 wherein each of the at least one delay control signal is generated by selectively coupling a respective one of the delay control inputs to a reference voltage.
Claim 5
Dependent Claim
79 words
The synchronous memory device of claim 1 wherein the adjustable time delay circuit comprises: a plurality of passgates arranged in columns, each column having a different number of passgates than any other column in the time delay circuit, the passgates in the column having the highest number of passgates in the delay circuit each coupled to a respective delay element having a respective delay value, the external clock signal coupled to and passing through each of the delay elements.
Claim 6
Dependent Claim
52 words
The synchronous memory device of claim 1 wherein the number of control inputs to the delay circuit is n, the number of columns in the time delay circuit is n, and the number of passgates in the column having the highest number of passgates in the delay circuit is 2 n .
Claim 7
Dependent Claim
19 words
The synchronous memory device of claim 1 wherein the synchronous memory device comprises a synchronous dynamic random access memory.
Claim 8
Dependent Claim
205 words
The synchronous memory device of claim 1 wherein the adjustable time delay circuit comprises: a plurality of delay elements having respective delay values; and N sets of passgates, each of the passgates having a control terminal structured to control the conductive state of the passgate, the passgates in each set being arranged in pairs in which one passgate in each pair has its control terminal coupled so that the passgate is rendered conductive responsive to the at least one control signal and the other passgate in each pair has its control terminal coupled so that the passgate is rendered conductive responsive to a compliment of the at least one control signal, the passgates in each pair having respective output terminals coupled to each other, the passgates in the Nth set being coupled in series with a respective one of the delay elements, and each series combination of one of the passgates in the Nth set and one of the delay elements being coupled to receive the clock signal, the passgates in each set other than the Nth set being coupled to the output terminals of a pair of passgates in an N+1 set, and the passgates in a first set generating the delayed clock signal.
Claim 9
Dependent Claim
228 words
A synchronous memory device comprising: a data bus having a plurality of data bus terminals; a clock terminal receiving an external clock signal; an address decoder; a control logic circuit structured to generate control signals responsive to memory commands; a memory-cell array coupled to the address decoder and the control logic circuit; a data output buffer coupled to a data bus; a data path coupled between the memory-cell array and the data output buffer, the data path circuit including for each bit of the data bus a data path circuit comprising: an adjustable time delay circuit having at least one delay control input, each delay control input coupled to receive a respective delay control signal, the time delay circuit coupled to receive the external clock signal and to generate a delayed clock signal, the time between when the external clock signal changes state and when the delayed clock signal changes state being determined by the at least one delay control signal applied to respective delay control inputs, and a data passing circuit having a data input terminal coupled to the memory-cell array and a data output terminal coupled to the data output buffer, the data passing circuit receiving the delayed clock signal and being structured to pass a data signal from the data input terminal to the data bus terminal responsive to the delayed clock signal changing state.
Claim 10
Dependent Claim
228 words
A synchronous memory device comprising: a data bus having a plurality of data bus terminals; a clock terminal receiving an external clock signal; an address decoder; a control logic circuit structured to generate control signals responsive to memory commands; a memory-cell array coupled to the address decoder and the control logic circuit; a data output buffer coupled to a data bus; a data path coupled between the memory-cell array and the data output buffer, the data path circuit including for each bit of the data bus a data path circuit comprising: an adjustable time delay circuit having at least one delay control input, each delay control input coupled to receive a respective delay control signal, the time delay circuit coupled to receive the external clock signal and to generate a delayed clock signal, the time between when the external clock signal changes state and when the delayed clock signal changes state being determined by the at least one delay control signal applied to respective delay control inputs, and a data passing circuit having a data input terminal coupled to the memory-cell array and a data output terminal coupled to the data output buffer, the data passing circuit receiving the delayed clock signal and being structured to pass a data signal from the data input terminal to the data bus terminal responsive to the delayed clock signal changing state.
Claim 11
Dependent Claim
44 words
The synchronous memory device of claim 8 wherein the data input terminal of the data passing circuit is coupled to the memory-cell array, and the data output terminal of the data passing circuit is coupled to a respective one of the data bus terminals.
Claim 12
Dependent Claim
34 words
The synchronous memory device of claim 8 wherein each of the at least one delay control signal is generated by selectively coupling a respective one of the delay control inputs to a reference voltage.
Claim 13
Dependent Claim
79 words
The synchronous memory device of claim 8 wherein the adjustable time delay circuit comprises: a plurality of passgates arranged in columns, each column having a different number of passgates than any other column in the time delay circuit, the passgates in the column having the highest number of passgates in the delay circuit each coupled to a respective delay element having a respective delay value, the external clock signal coupled to and passing through each of the delay elements.
Claim 14
Dependent Claim
52 words
The synchronous memory device of claim 8 wherein the number of control inputs to the delay circuit is n, the number of columns in the time delay circuit is n, and the number of passgates in the column having the highest number of passgates in the delay circuit is 2 n .
Claim 15
Dependent Claim
19 words
The synchronous memory device of claim 8 wherein the synchronous memory device comprises a synchronous dynamic random access memory.
Claim 16
Dependent Claim
205 words
The synchronous memory device of claim 8 wherein the adjustable time delay circuit comprises: a plurality of delay elements having respective delay values; and N sets of passgates, each of the passgates having a control terminal structured to control the conductive state of the passgate, the passgates in each set being arranged in pairs in which one passgate in each pair has its control terminal coupled so that the passgate is rendered conductive responsive to the at least one control signal and the other passgate in each pair has its control terminal coupled so that the passgate is rendered conductive responsive to a compliment of the at least one control signal, the passgates in each pair having respective output terminals coupled to each other, the passgates in the Nth set being coupled in series with a respective one of the delay elements, and each series combination of one of the passgates in the Nth set and one of the delay elements being coupled to receive the clock signal, the passgates in each set other than the Nth set being coupled to the output terminals of a pair of passgates in an N+1 set, and the passgates in a first set generating the delayed clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-12-23 | 2006-06-24 | 2006-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-23 | 2010-06-24 | 2010-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-23 | 2014-06-24 | 2014-12-24 | $7700.00 | Window Closed / Lapsed |