High speed CMOS driver circuit

Claim 2

A high-speed CMOS circuit for driving an input signal, said CMOS circuit providing, at an output node, an output signal which is coupled to a receiver circuit via a transmission line characterized by a lumped capacitive load, said CMOS circuit comprising: a P-channel, field-effect, output driver transistor connected between a high logic level reference voltage and the output node, the "on" impedance (R ON ) of said P-channel output driver transistor being matched to the characteristic impedance of the transmission line, said P-channel output driver transistor having a control gate; an N-channel, field-effect, output driver transistor connected between a low logic level reference voltage and the output node, the "on" impedance (R ON ) of said N-channel output driver transistor being matched to the characteristic impedance of the transmission line, said N-channel output driver transistor having a control gate; a predriver circuit which, in response to the input signal and an output enable signal, provides blanking pulses to both control gates so as to tri-state the driver output during periods of input signal transition from low-to-high and high-to-low states, said blanking pulses being created by separate input signal paths for each of the output driver transistors; one path having as an input the true output of an XOR gate; the other path having as an input the complement output of the XOR gate, said XOR gate having a pair of inputs, one of which is the input signal, the other being a delayed version of the same.

Claim 3

The high-speed CMOS circuit of claim 1 wherein an output enable signal forces both the N-channel and P-channel output drivers to a high-impedance state.

Claim 4

A high-speed CMOS circuit for driving an input signal, said CMOS circuit providing, at an output node, an output signal which is coupled to a receiver circuit via a transmission line characterized by a lumped capacitive load, said CMOS circuit comprising: a P-channel, field-effect, output driver transistor connected between a high logic level reference voltage and the output node, the "on" impedance (R ON ) of said P-channel output driver transistor being matched to the characteristic impedance of the transmission line, said P-channel output driver transistor having a control gate; an N-channel, field-effect, output driver transistor connected between a low logic level reference voltage and the output node, the "on" impedance (R ON ) of said N-channel output driver transistor being matched to the characteristic impedance of the transmission line, said N-channel output driver transistor having a control gate; a predriver circuit which drives both control gates in response to the input signal and an output enable signal in a coordinated sequence that ensures that both output driver transistors are never simultaneously "on" during periods of input signal transition from low-to-high and high-to-low states, said predriver circuit having a first signal path for the P-channel transistor control gate and a second signal path for the N-channel transistor control gate, said first and second signal paths having identical multiplexers and P-channel gate signal which generate identical signal delays.

Claim 5

A high-speed CMOS circuit for driving an input signal, said CMOS circuit providing, at an output node, an output signal which is coupled to a receiver circuit via a transmission line characterized by a lumped capacitive load, said CMOS circuit comprising: a P-channel, field-effect, output driver transistor connected between a high logic level reference voltage and the output node, the "on" impedance (R ON ) of said P-channel output driver transistor being matched to the characteristic impedance of the transmission line, said P-channel output driver transistor having a control gate; an N-channel, field-effect, output driver transistor connected between a low logic level reference voltage and the output node, the "on" impedance (R ON ) of said N-channel output driver transistor being matched to the characteristic impedance of the transmission line, said N-channel output driver transistor having a control gate; a predriver circuit which drives both control gates in response to the input signal and an output enable signal in a coordinated sequence that ensures that both output driver transistors are never simultaneously "on" during periods of input signal transition from low-to-high and high-to-low states, said predriver circuit having a first signal path for the P-channel transistor control gate and a second signal path for the N-channel transistor control gate, said first and second signal paths having identical multiplexers and P-channel gate signal which generate identical signal delays.

Claim 6

The high-speed CMOS circuit of claim 3 wherein each multiplexer is formed by a "wired OR" configuration of two tri-state inverters.

Claim 7

The high-speed CMOS circuit of claim 4 wherein an output enable signal forces both the N-channel and P-channel output drivers to a high-impedance state.

Claim 8

A high-speed CMOS circuit for driving an input signal, said CMOS circuit providing, at an output node, an output signal which is coupled to a receiver circuit via a transmission line characterized by a lumped capacitive load, said CMOS circuit comprising: a P-channel, field-effect, output driver transistor connected between a high logic level reference voltage and the output node, the "on" impedance (R ON ) of said P-channel output driver transistor being matched to the characteristic impedance of the transmission line, said P-channel output driver transistor having a control gate; an N-channel, field-effect, output driver transistor connected between a low logic level reference voltage and the output node, the "on" impedance (R ON ) of said N-channel output driver transistor being matched to the characteristic impedance of the transmission line, said N-channel output driver transistor having a control gate; a predriver circuit which drives both control gates in response to the input signal and an output enable signal in a coordinated sequence that ensures that both output driver transistors are never simultaneously "on" during periods of input signal transition from low-to-high and high-to-low states; said predriver circuit having a first signal path for the P-channel transistor control gate and a second signal path for the N-channel transistor control gate; each gate signal path having a set of series-connected logic gates, the gates of one path being cross-coupled with the state of the other path and arranged to as to provide a delay in one of the paths during periods of input signal transition, so that an output driver transistor that is "on" at the onset of such a period is shut "off" prior to the other output driver transistor being turned on; the logic gates of said first signal path comprising a first NAND gate and a first NOR gate, and the logic gates of said second signal path comprising a second NAND gate and a second NOR gate; said first NAND gate having as inputs said input signal and the output of said second NAND gate; said first NOR gate having as inputs the output of said first NAND gate and the complement of said output enable signal; said second NAND gate having as inputs the output of said second NOR gate and said output enable signal; and said second NOR gate having as inputs said input signal and the output of said first NOR gate.

Claim 9

A high-speed CMOS circuit for driving an input signal, said CMOS circuit providing, at an output node, an output signal which is coupled to a receiver circuit via a transmission line characterized by a lumped capacitive load, said CMOS circuit comprising: a P-channel, field-effect, output driver transistor connected between a high logic level reference voltage and the output node, the "on" impedance (R ON ) of said P-channel output driver transistor being matched to the characteristic impedance of the transmission line, said P-channel output driver transistor having a control gate; an N-channel, field-effect, output driver transistor connected between a low logic level reference voltage and the output node, the "on" impedance (R ON ) of said N-channel output driver transistor being matched to the characteristic impedance of the transmission line, said N-channel output driver transistor having a control gate; a predriver circuit which drives both control gates in response to the input signal and an output enable signal in a coordinated sequence that ensures that both output driver transistors are never simultaneously "on" during periods of input signal transition from low-to-high and high-to-low states; said predriver circuit having a first signal path for the P-channel transistor control gate and a second signal path for the N-channel transistor control gate; each gate signal path having a set of series-connected logic gates, the gates of one path being cross-coupled with the state of the other path and arranged to as to provide a delay in one of the paths during periods of input signal transition, so that an output driver transistor that is "on" at the onset of such a period is shut "off" prior to the other output driver transistor being turned on; the logic gates of said first signal path comprising a first NAND gate and a first NOR gate, and the logic gates of said second signal path comprising a second NAND gate and a second NOR gate; said first NAND gate having as inputs said input signal and the output of said second NAND gate; said first NOR gate having as inputs the output of said first NAND gate and the complement of said output enable signal; said second NAND gate having as inputs the output of said second NOR gate and said output enable signal; and said second NOR gate having as inputs said input signal and the output of said first NOR gate.

Claim 10

The high-speed CMOS circuit of claim 6, wherein said first gate signal path further comprises a first inverter, which is placed in series between the output of said first NOR gate and the gate of said P-channel output driver transistor, and said second gate signal path further comprises a second inverter, which is placed in series between the output of said second NAND gate and the gate of said N-channel output driver transistor.