Programmable multiple I/O interface controller

Claim 2

Apparatus for transferring a plurality of data values between a first data processing device and a second data processing device, wherein said first data processing device transmits a first plurality of control signals corresponding to a first protocol and said second data processing device receives a second plurality of control signals corresponding to a second protocol, comprising: first control means, coupled to said first data processing device, for receiving said first plurality of control signals from said first data processing device through any one of a first plurality of physical interfaces wherein one of said first plurality of physical interfaces is different from another one of said first plurality of physical interfaces; translation means, coupled to said first control means, for translating said plurality of first control signals to said plurality of second control signals; second control means, coupled to said translation means, for transmitting said second plurality of control signals to said second data processing device through any one of a second plurality of physical interfaces wherein one of said second plurality of physical interfaces is different from another one of said second plurality of physical interfaces; first data means, coupled to said first data processing device, for receiving said plurality of data values from said first data processing device; and second data means, coupled to said first data means, for transmitting said plurality of data values to said second data processing device.

Claim 3

The apparatus of claim 1, wherein said first plurality of control signals comprises a control signal and a further control signal, and said first control means comprises: means for receiving said control signal; means for receiving said further control signal; comparison means for comparing said control signal to said further control signal; and means, responsive to said comparison means, for selectively inhibiting said first data means from receiving said plurality of data values from said first data processing device.

Claim 4

Apparatus for transferring a plurality of data values between a first data processing device and a second data processing device, each of said data values comprising a first data value and a second data value wherein said first data processing device transmits a first plurality of control signals corresponding to a first protocol and said second data processing device receives a second plurality of control signals corresponding to a second protocol, comprising: first control means, coupled to said first data processing device, for receiving said first plurality of control signals from said first data processing device; translation means, coupled to said first control means, for translating said plurality of first control signals to said plurality of second control signals; second control means, coupled to said translation means, for transmitting said second plurality of control signals to said second data processing device; first data means, coupled to said first data processing device, for receiving said plurality of data values from said first data processing device; and second data means, coupled to said first data means, for transmitting said plurality of data values to said second data processing device; said first data means further comprising: latch means for sequentially receiving said first data value, transmitting said first data value, receiving said second data value and transmitting said second data value; synchronization register means, coupled to said latch means, for sequentially receiving said first data value and said second data value to form a packed data value, and data register means, coupled to said synchronization register means, for receiving said packed data value from said synchronization register means.

Claim 5

Apparatus for transferring a plurality of data values between a first data processing device and a second data processing device, each of said data values comprising a first data value and a second data value wherein said first data processing device transmits a first plurality of control signals corresponding to a first protocol and said second data processing device receives a second plurality of control signals corresponding to a second protocol, comprising: first control means, coupled to said first data processing device, for receiving said first plurality of control signals from said first data processing device; translation means, coupled to said first control means, for translating said plurality of first control signals to said plurality of second control signals; second control means, coupled to said translation means, for transmitting said second plurality of control signals to said second data processing device; first data means, coupled to said first data processing device, for receiving said plurality of data values from said first data processing device; and second data means, coupled to said first data means, for transmitting said plurality of data values to said second data processing device; said first data means further comprising: latch means for sequentially receiving said first data value, transmitting said first data value, receiving said second data value and transmitting said second data value; synchronization register means, coupled to said latch means, for sequentially receiving said first data value and said second data value to form a packed data value, and data register means, coupled to said synchronization register means, for receiving said packed data value from said synchronization register means.

Claim 6

The apparatus of claim 3, wherein said packed data value comprises a most significant portion corresponding to said first data value and a least significant portion corresponding to said second data value.

Claim 7

The apparatus of claim 3, wherein said packed data value comprises a most significant portion corresponding to said second data value and a least significant portion corresponding to said first data value.

Claim 8

The apparatus of claim 1, wherein said translation means includes: memory means having a plurality of memory locations containing respective ones of said plurality of second control signals, and further comprising: receiving means for receiving at least one of said first plurality of control signals; mapping means coupled to said receiving means and said memory means, for mapping said one control signal to at least one of said plurality of memory locations and for transmitting at least one of said plurality of second control signals to said second control means.

Claim 9

Apparatus for transferring a plurality of data values between a first data processing device and a second data processing device, wherein said first data processing device transmits a first plurality of control signals corresponding to a first protocol and said second data processing device receives a second plurality of control signals corresponding to a second protocol, comprising: first control means, coupled to said first data processing device, for receiving said first plurality of control signals from said first data processing device; translation means, coupled to said first control means, for translating said plurality of first control signals to said plurality of second control signals; second control means, coupled to said translation means, for transmitting said second plurality of control signals to said second data processing device; first data means, coupled to said first data processing device, for receiving said plurality of data values from said first data processing device; and second data means, coupled to said first data means, for transmitting said plurality of data values to said second data processing device; said apparatus further including circuitry for receiving a data ready strobe from a data device, for returning an acknowledgement strobe to said data device, and for generating a synchronization signal, said synchronization signal synchronized with a system clock signal, said circuitry comprising: edge detection means, responsive to a transition of said data ready strobe, for storing an edge detection logic value in said edge detection means; strobe acknowledgement means, coupled to said edge detection means and responsive to said edge detection logic value, for asynchronously transmitting said acknowledgement strobe to said data device; clock synchronization means, coupled to said edge detection means and responsive to said edge detection logic value and to a transition of said system clock signal, for generating said synchronization signal.

Claim 10

Apparatus for transferring a plurality of data values between a first data processing device and a second data processing device, wherein said first data processing device transmits a first plurality of control signals corresponding to a first protocol and said second data processing device receives a second plurality of control signals corresponding to a second protocol, comprising: first control means, coupled to said first data processing device, for receiving said first plurality of control signals from said first data processing device; translation means, coupled to said first control means, for translating said plurality of first control signals to said plurality of second control signals; second control means, coupled to said translation means, for transmitting said second plurality of control signals to said second data processing device; first data means, coupled to said first data processing device, for receiving said plurality of data values from said first data processing device; and second data means, coupled to said first data means, for transmitting said plurality of data values to said second data processing device; said apparatus further including circuitry for receiving a data ready strobe from a data device, for returning an acknowledgement strobe to said data device, and for generating a synchronization signal, said synchronization signal synchronized with a system clock signal, said circuitry comprising: edge detection means, responsive to a transition of said data ready strobe, for storing an edge detection logic value in said edge detection means; strobe acknowledgement means, coupled to said edge detection means and responsive to said edge detection logic value, for asynchronously transmitting said acknowledgement strobe to said data device; clock synchronization means, coupled to said edge detection means and responsive to said edge detection logic value and to a transition of said system clock signal, for generating said synchronization signal.

Claim 11

The apparatus of claim 7, wherein said data device provides data with said data ready strobe and said data is stored in the first data means responsive to said data ready strobe.

Claim 12

The apparatus of claim 1, wherein said first data processing device and said second data processing device are each computer processors.

Claim 13

The apparatus of claim 1, wherein said first data processing device is an input/output (I/O) device and said second data processing device is an I/O channel.

Claim 14

The apparatus of claim 1, wherein said first data processing device is an input/output (I/O) channel and said second data processing device is an I/O device.

Claim 19

Apparatus for recognizing one of a first event and a second event wherein said first event and said second event are each signified by a respective signal, and for executing a task associated with one of said first event and said second event, respectively, comprising: first storage means for storing a first reference value corresponding to said first event; second storage means for storing a second reference value corresponding to said second event; sequencer means, coupled to said first storage means and said second storage means, for receiving said first reference value and said second reference value, and for detecting said signal which signifies said first event or said signal which signifies said second event; further storage means coupled to said first storage means and said second storage means for storing a first task reference value corresponding to said first event and a second task reference value corresponding to said second event; and means coupled to said further storage means and responsive to one of said first event and said second event for respectively executing one of said task corresponding to said first task reference value and said task corresponding to said second task reference value.

Claim 20

Apparatus for recognizing one of a first event and a second event wherein said first event and said second event are each signified by a respective signal, and for executing a task associated with one of said first event and said second event, respectively, comprising: first storage means for storing a first reference value corresponding to said first event; second storage means for storing a second reference value corresponding to said second event; sequencer means, coupled to said first storage means and said second storage means, for receiving said first reference value and said second reference value, and for detecting said signal which signifies said first event or said signal which signifies said second event; further storage means coupled to said first storage means and said second storage means for storing a first task reference value corresponding to said first event and a second task reference value corresponding to said second event; and means coupled to said further storage means and responsive to one of said first event and said second event for respectively executing one of said task corresponding to said first task reference value and said task corresponding to said second task reference value.

Claim 21

The apparatus of claim 14 wherein said first storage means and said second storage means are an interrupt state word.

Claim 22

The apparatus of claim 14 wherein said task reference value is stored in a task reference word.

Claim 23

The apparatus of claim 14, wherein said first storage means and said second storage means each further include means for storing a plurality of reference values corresponding to a plurality of events.

Claim 24

The apparatus of claim 17 wherein said sequencer means further includes means for receiving at least one of said plurality of reference values corresponding to said plurality of events.

Claim 25

An I/O interface controller for transferring communications between a host processor and an I/O device, comprising: host side means for communicating with said host processor through any one of a first plurality of physical interfaces wherein one of a first plurality of physical interfaces is different from another one of said first plurality of physical interfaces and wherein said host processor communicates using a first communications protocol; peripheral side means for communicating with said I/O device through any one of a second plurality of physical interfaces wherein one of said second plurality of physical interfaces is different from another one of said second plurality of physical interfaces and wherein said I/O device communicates using a second communications protocol; means for independently programming said host side means to communicate with said host processor using said first communications protocol and for programming said peripheral side means to communicate with said I/O device using said second communications protocol, respectively; and means for translating communications between said first communications protocol and said second communications protocol and for transferring communications between said host side means and said peripheral side means.

Claim 26

An I/O interface controller for transferring communications between a host processor and an I/O device, comprising: host side means for communicating with said host processor through any one of a first plurality of physical interfaces wherein one of a first plurality of physical interfaces is different from another one of said first plurality of physical interfaces and wherein said host processor communicates using a first communications protocol; peripheral side means for communicating with said I/O device through any one of a second plurality of physical interfaces wherein one of said second plurality of physical interfaces is different from another one of said second plurality of physical interfaces and wherein said I/O device communicates using a second communications protocol; means for independently programming said host side means to communicate with said host processor using said first communications protocol and for programming said peripheral side means to communicate with said I/O device using said second communications protocol, respectively; and means for translating communications between said first communications protocol and said second communications protocol and for transferring communications between said host side means and said peripheral side means.

Claim 27

An I/O interface controller for enabling communications, including transferring data and a plurality of control signals, between a host processor and an I/O device, comprising: a plurality of registers, including at least one register for establishing control, including exchanging at least one of said plurality of control signals, with said I/O device; at least one register for establishing control, including exchanging at least one of said plurality of control signals, with said host processor; and at least one register for transferring data between said I/O device and said host processor; an arithmetic logic unit for processing said plurality of control signals and said data; and a condition code multiplexer for examining the contents of said plurality of registers and for transmitting to said arithmetic logic unit a plurality of conditioning signals indicating the contents of said plurality of registers, wherein said arithmetic logic unit performs predetermined operations responsive to said conditioning signals.

Claim 28

An I/O interface controller for enabling communications, including transferring data and a plurality of control signals, between a host processor and an I/O device, comprising: a plurality of registers, including at least one register for establishing control, including exchanging at least one of said plurality of control signals, with said I/O device; at least one register for establishing control, including exchanging at least one of said plurality of control signals, with said host processor; and at least one register for transferring data between said I/O device and said host processor; an arithmetic logic unit for processing said plurality of control signals and said data; and a condition code multiplexer for examining the contents of said plurality of registers and for transmitting to said arithmetic logic unit a plurality of conditioning signals indicating the contents of said plurality of registers, wherein said arithmetic logic unit performs predetermined operations responsive to said conditioning signals.

Claim 29

The I/O interface controller of claim 20, wherein said I/O interface controller is implemented in a single integrated circuit.

Claim 30

An I/O interface controller for receiving at least one of a plurality of host commands from a host processor and for transferring data between the host processor and an I/O device, comprising: host interface means for transferring data between said host interface means and said host processor through any one of a first plurality of physical interfaces wherein one of said first plurality of physical interfaces is different from another one of said first plurality of physical interfaces responsive to said one host command; peripheral interface means for transferring data between said peripheral interface means and said I/O device through any one of a second plurality of physical interfaces wherein one of said second plurality of physical interfaces is different from another one of said second plurality of physical interfaces responsive to at least one of a plurality of peripheral commands; host queue means, coupled to the host interface means, for receiving said one host command from the host processor; sequencer means coupled to said host queue means for evaluating said one host command, for mapping said one host command to at least one of said plurality of peripheral commands and for transmitting said one peripheral command to said peripheral interface means.

Claim 31

An I/O interface controller for receiving at least one of a plurality of host commands from a host processor and for transferring data between the host processor and an I/O device, comprising: host interface means for transferring data between said host interface means and said host processor through any one of a first plurality of physical interfaces wherein one of said first plurality of physical interfaces is different from another one of said first plurality of physical interfaces responsive to said one host command; peripheral interface means for transferring data between said peripheral interface means and said I/O device through any one of a second plurality of physical interfaces wherein one of said second plurality of physical interfaces is different from another one of said second plurality of physical interfaces responsive to at least one of a plurality of peripheral commands; host queue means, coupled to the host interface means, for receiving said one host command from the host processor; sequencer means coupled to said host queue means for evaluating said one host command, for mapping said one host command to at least one of said plurality of peripheral commands and for transmitting said one peripheral command to said peripheral interface means.

Claim 32

The I/O interface controller of claim 22 further comprising: command initiate queue means, coupled to the peripheral interface means, for receiving said one host command from said host queue means; wherein said sequencer means evaluates said one host command from said command initiate queue means.

Claim 35

Apparatus for receiving a host command from a host processor and for transferring data between said host processor and an I/O device, comprising: a) host interfacing means for receiving at least one of said plurality of host commands from said host processor through any one of a first plurality of physical interfaces wherein one of said first plurality of physical interfaces is different from another one of said first plurality of physical interfaces; b) linking means for linking said received host command into a first queue; c) translating means for translating said received host command into at least one I/O device command; d) command transferring means for transferring said I/O device command to said I/O device through any one of a second plurality of physical interfaces wherein one of said second plurality of physical interfaces is different from another one of said second plurality of physical interfaces; and e) data transferring means coupled to said I/O device and to said host processor for transferring data between said I/O device and said host processor.

Claim 36

Apparatus for receiving a host command from a host processor and for transferring data between said host processor and an I/O device, comprising: a) host interfacing means for receiving at least one of said plurality of host commands from said host processor through any one of a first plurality of physical interfaces wherein one of said first plurality of physical interfaces is different from another one of said first plurality of physical interfaces; b) linking means for linking said received host command into a first queue; c) translating means for translating said received host command into at least one I/O device command; d) command transferring means for transferring said I/O device command to said I/O device through any one of a second plurality of physical interfaces wherein one of said second plurality of physical interfaces is different from another one of said second plurality of physical interfaces; and e) data transferring means coupled to said I/O device and to said host processor for transferring data between said I/O device and said host processor.

Claim 39

The method of claim 26 wherein step c) includes the additional step of transferring said received host command from said first queue to a second queue and wherein step d) includes the step of executing at least one I/O command corresponding to said received host command located in said second queue.

Claim 40

The method of claim 26 wherein step d) is preceded by the step of transmitting a communication establishment signal to said I/O device by said interface controller.

Claim 41

The apparatus of claim 1, wherein said translation means translates said plurality of first control signals to said plurality of second control signals by executing a respective one of a plurality of program routines based upon a respective one of said plurality of first control signals which is received.

Claim 42

An I/O interface controller in accordance with claim 19, wherein said means for translating communications translates said plurality of first control signals to said plurality of second control signals by executing a respective one of a plurality of program routines based upon a respective one of said plurality of first control signals which is received.

Claim 43

An I/O interface controller in accordance with claim 22, further including translation means which translates said plurality of host commands to said plurality of peripheral commands by executing a respective one of a plurality of program routines based upon a respective one of said plurality of host commands which is received.

Claim 44

A method of receiving a host command from a host processor in accordance with claim 24, wherein step c) includes the step of translating said host command into at least one I/O device commands by executing a respective one of a plurality of program routines based upon said host command which is received.

Claim 45

Apparatus for receiving a host command from a host processor in accordance with claim 25, wherein said translating means translates said host command to said I/O device command by executing a respective one of a plurality of program routines based upon said host command which is received.