US5311481A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wordline driver circuit having a directly gated pull-down device
Assignee: Micron Technology Inc
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Filing: 1992-12-17
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Granted: 1994-05-10
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Expires: 2012-12-17
Abstract
Abstract The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.
Inventors
- 👤 Stephen L. Casper
- 👤 Adrian Ong
- 👤 Paul S. Zagar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:42
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/08
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
149 words
A memory device, comprising: a) an output node; b) decode circuitry for determining a logic state of said output node, said decode circuitry generating a primary and a secondary predecode signal; c) a driving circuit for driving the output node to an inactive logic state when actuated, said driving circuit directly actuated by a corresponding primary predecode signal; d) a latching circuit for monitoring the logic state of the output node and latching the output node to said inactive logic state; e) an inverter circuit for inverting said primary predecode signal to said output node; and f) a pass device for transmitting said primary predecode signal to said inverter when actuated by said secondary predecode signal, such that when said driving circuit is deactuated by said primary predecode signal and said pass device is actuated by said secondary predecode signal said wordline is driven to an active logic state.
Claim 2
Dependent Claim
149 words
A memory device, comprising: a) an output node; b) decode circuitry for determining a logic state of said output node, said decode circuitry generating a primary and a secondary predecode signal; c) a driving circuit for driving the output node to an inactive logic state when actuated, said driving circuit directly actuated by a corresponding primary predecode signal; d) a latching circuit for monitoring the logic state of the output node and latching the output node to said inactive logic state; e) an inverter circuit for inverting said primary predecode signal to said output node; and f) a pass device for transmitting said primary predecode signal to said inverter when actuated by said secondary predecode signal, such that when said driving circuit is deactuated by said primary predecode signal and said pass device is actuated by said secondary predecode signal said wordline is driven to an active logic state.
Claim 3
Independent Claim
144 words
A method for driving a wordline to a potential having an inactive logic state, the method comprising the following steps: a) generating a primary predecode signal having an actuation potential; b) actuating a driving device with said primary predecode signal having a full value of said actuation potential; c) driving the wordline to the potential having the inactive logic state through the driving device; d) generating a latch signal in response to the inactive logic state on the wordline, said latch signal having a potential capable of actuating latch circuitry; e) actuating said latch circuitry with said latch signal; f) latching the wordline to the inactive logic state through said latch circuitry; g) actuating a precharge device with said primary predecode signal having the full value of said actuation potential; and h) pulling a serial node to a precharge potential through said precharge device.
Claim 4
Independent Claim
144 words
A method for driving a wordline to a potential having an inactive logic state, the method comprising the following steps: a) generating a primary predecode signal having an actuation potential; b) actuating a driving device with said primary predecode signal having a full value of said actuation potential; c) driving the wordline to the potential having the inactive logic state through the driving device; d) generating a latch signal in response to the inactive logic state on the wordline, said latch signal having a potential capable of actuating latch circuitry; e) actuating said latch circuitry with said latch signal; f) latching the wordline to the inactive logic state through said latch circuitry; g) actuating a precharge device with said primary predecode signal having the full value of said actuation potential; and h) pulling a serial node to a precharge potential through said precharge device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-09 | 1997-11-08 | 1998-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-09 | 2001-11-08 | 2002-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-09 | 2005-11-08 | 2006-05-10 | $7700.00 | Window Closed / Lapsed |