US5065361A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory integrated circuit
Assignee: Toshiba Corp
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Filing: 1989-12-05
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Granted: 1991-11-12
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Expires: 2009-12-05
Abstract
Abstract A semiconductor memory integrated circuit is made up of a decoder, a memory matrix, and a decode output buffer selectively receiving a first or second power source voltage. The decode output buffer is provided between the decoder and the memory matrix, and includes an inverter circuit for inverting the output signal of the decoder, and a MOS transistor of a depletion mode, the gate of which is connected to the output terminal of the inverter, the first end of which is connected to a supply node of the first or second power source voltage, and the second end of which is connected to a power voltage supply node of the inverter circuit.
Inventors
- 👤 Makoto Yoshizawa
- 👤 Tadashi Maruyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 00:24
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/30
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
215 words
A semiconductor memory integrated circuit comprising: a decoder; a memory matrix; a selector for receiving a first power source voltage and a second power source voltage, and for selecting said first or second power source voltage; and a decode output buffer for receiving said first or second power source voltage from said selector, said decode output buffer being provided between said decoder and said memory matrix, and including an inverter circuit, having a first power source terminal connected to a reference power source voltage and a second power source terminal, for inverting an output signal of said decoder, a first MOS transistor of a depletion mode, the gate of which is connected to the output terminal of said inverter circuit, the first end of which is connected to said first or second power source voltage selected by said selector, and the second end of which is connected to said second power source terminal of said inverter circuit, and a second MOS transistor of the depletion mode, the first end of which is connected to said first power source voltage, and the second end of which is connected to said second power source terminal of said inverter circuit, the conduction of said second MOS transistor being controlled in accordance with the output signal of said decoder.
Claim 2
Dependent Claim
215 words
A semiconductor memory integrated circuit comprising: a decoder; a memory matrix; a selector for receiving a first power source voltage and a second power source voltage, and for selecting said first or second power source voltage; and a decode output buffer for receiving said first or second power source voltage from said selector, said decode output buffer being provided between said decoder and said memory matrix, and including an inverter circuit, having a first power source terminal connected to a reference power source voltage and a second power source terminal, for inverting an output signal of said decoder, a first MOS transistor of a depletion mode, the gate of which is connected to the output terminal of said inverter circuit, the first end of which is connected to said first or second power source voltage selected by said selector, and the second end of which is connected to said second power source terminal of said inverter circuit, and a second MOS transistor of the depletion mode, the first end of which is connected to said first power source voltage, and the second end of which is connected to said second power source terminal of said inverter circuit, the conduction of said second MOS transistor being controlled in accordance with the output signal of said decoder.
Claim 3
Dependent Claim
225 words
A semiconductor memory integrated circuit comprising: a decoder; a memory matrix; a selector for receiving a first power source voltage and a second power source voltage, and for selecting said first or second power source voltage; and a decode output buffer for receiving said first or second power source voltage from said selector, said decode output buffer being provided between said decoder and said memory matrix, and including an inverter circuit, having a first power source terminal connected to a reference power source voltage and a second power source terminal, for inverting an output signal of said decoder, a first MOS transistor of a depletion mode, the first end of which is connected to the output terminal of said inverter circuit and the gate of which is supplied with a control signal, a second MOS transistor of the depletion mode, the first end of which is connected to said first or second power source voltage selected by said selector, and the gate of which is connected to the second end of said first transistor, and a third MOS transistor, the first end of which is connected to the second end of said second MOS transistor, the second end of which is connected to the second end of said first MOS transistor, and the gate of which is supplied with the output signal of said decoder.
Claim 4
Dependent Claim
225 words
A semiconductor memory integrated circuit comprising: a decoder; a memory matrix; a selector for receiving a first power source voltage and a second power source voltage, and for selecting said first or second power source voltage; and a decode output buffer for receiving said first or second power source voltage from said selector, said decode output buffer being provided between said decoder and said memory matrix, and including an inverter circuit, having a first power source terminal connected to a reference power source voltage and a second power source terminal, for inverting an output signal of said decoder, a first MOS transistor of a depletion mode, the first end of which is connected to the output terminal of said inverter circuit and the gate of which is supplied with a control signal, a second MOS transistor of the depletion mode, the first end of which is connected to said first or second power source voltage selected by said selector, and the gate of which is connected to the second end of said first transistor, and a third MOS transistor, the first end of which is connected to the second end of said second MOS transistor, the second end of which is connected to the second end of said first MOS transistor, and the gate of which is supplied with the output signal of said decoder.
Claim 5
Dependent Claim
307 words
A semiconductor memory integrated circuit comprising: a decoder; a memory matrix; a selector for receiving a first power source voltage and a second power source voltage, and for selecting said first or second power source voltage; and a decode output buffer for receiving said first or second power source voltage from said selector, said decode output buffer being provided between said decoder and said memory matrix, and including an inverter circuit, having a first power source terminal connected to a reference power source voltage and a second power source terminal, for inverting an output signal of said decoder, a first MOS transistor of a depletion mode, the first end of which is connected to the output terminal of said inverter circuit, and the gate of which is supplied with a control signal, a second MOS transistor of the depletion mode, the first end of which is connected to said first or second power source voltage selected by said selector, and the gate of which is connected to the second end of said first transistor, a third MOS transistor, the first end of which is connected to the second end of said second MOS transistor, the second end of which is connected to the second end of said first MOS transistor, and the gate of which is supplied with the output signal of said decoder, a fourth MOS transistor, the first end of which is connected to said first power source voltage, and the gate of which is supplied with the output signal of said inverter circuit, and a fifth MOS transistor, the first end of which is connected to the second end of said fourth MOS transistor, the second end of which is connected to the first end of said third MOS transistor, and the gate of which is supplied with the output signal of said decoder.
Claim 6
Dependent Claim
307 words
A semiconductor memory integrated circuit comprising: a decoder; a memory matrix; a selector for receiving a first power source voltage and a second power source voltage, and for selecting said first or second power source voltage; and a decode output buffer for receiving said first or second power source voltage from said selector, said decode output buffer being provided between said decoder and said memory matrix, and including an inverter circuit, having a first power source terminal connected to a reference power source voltage and a second power source terminal, for inverting an output signal of said decoder, a first MOS transistor of a depletion mode, the first end of which is connected to the output terminal of said inverter circuit, and the gate of which is supplied with a control signal, a second MOS transistor of the depletion mode, the first end of which is connected to said first or second power source voltage selected by said selector, and the gate of which is connected to the second end of said first transistor, a third MOS transistor, the first end of which is connected to the second end of said second MOS transistor, the second end of which is connected to the second end of said first MOS transistor, and the gate of which is supplied with the output signal of said decoder, a fourth MOS transistor, the first end of which is connected to said first power source voltage, and the gate of which is supplied with the output signal of said inverter circuit, and a fifth MOS transistor, the first end of which is connected to the second end of said fourth MOS transistor, the second end of which is connected to the first end of said third MOS transistor, and the gate of which is supplied with the output signal of said decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-11 | 1995-05-13 | 1995-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-11 | 1999-05-13 | 1999-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-11 | 2003-05-13 | 2003-11-12 | $7700.00 | Window Closed / Lapsed |