EP0450871B1
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Interfaces for transmission lines
Assignee: Xerox Corp
•
Filing: 1991-03-28
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Granted: 1998-06-24
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Expires: 2011-03-28
Abstract
No abstract record available.
Inventors
- 👤 William F. Gunning
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 21:19
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/0175; H03K19/0185; H03K19/018557; H03K19/018571
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
145 words
An interface for interfacing VLSI CMOS binary circuits (11-13) to a terminated
transmission line (14) for binary communications between the circuits; the interface comprising drivers (16) for feeding binary signals from CMOS circuits (26) to a transmission line (14);
each driver including an N-channel transistor (25) having a drain coupled to the transmission line. a
source returned to ground, and a gate coupled to receive binary signals from one of the CMOS
circuits; characterised by the gate of the transistor being of chosen effective width and length, with its
width being plural orders of magnitude greater than its length, and by the interface being adapted to
provide output signals at signal levels providing a signal swing of about 0.8 - 1.4 V between a line-terminating
voltage level of about 1.2 - 2.0 V and a low voltage level of about 0.4 - 0 6 V.
Claim 2
Dependent Claim
206 words
An interface for interfacing a terminated transmission line (14) to VLSI CMOS binary
circuits (11-13) for binary communications between the circuits at signal levels providing a signal
swing of about 0.8 - 1.4 V between a line-terminating voltage level of about 1.2 - 2.0 V and a low
voltage level of about 0.4 - 0.6 V; the interface comprising receivers (17) for feeding binary signals from the transmission line (14) to the CMOS
circuits (11-13), characterised by each receiver including a N-channel transistor (31), a P-channel
transistor (32), means for supplying a reference voltage, and means (33) for supplying a bias
voltage; the N-channel transistor (31) having a source coupled to the transmission line. a drain. and a
gate coupled to the reference voltage; the P-channel transistor (32) having a source coupled to a
power supply, a drain coupled to the drain of the N-channel transistor, and a gate coupled to the bias
voltage; the bias voltage being selected to bias the P-channel transistor (32) for conduction: and the
reference voltage being selected for switching the N-channel transistor into and out of conduction as
the signal on the transmission line drops below and rises above, respectively, a decision threshold
near the center of the signal swing.
Claim 3
Dependent Claim
15 words
A composite interface incorporating the interface of claim 1 and the interface of
claim 2.
Claim 4
Dependent Claim
63 words
The interface of Claim 2 or 3, wherein each receiver further includes an amplifier
(35) coupled to the drains of the transistors (31, 32); and a flip-flop (36) coupled to the amplifier, the
flip-flop being prepared to switch from one state to another when the signal on the transmission line
(14) drops below and rises above, the decision threshold by a chosen amount.
Claim 5
Dependent Claim
94 words
The interface of any of claims 1, 3 or 4 wherein each driver further includes: a normally disabled switch means (51) coupled between the source and gate of said N-channel
transistor (25); and means (55-57) for enabling said switch means (51) temporarily whenever said transistor
(25) is being switched from a conductive state to a non-conductive state, thereby providing a
negative feedback path from the source to the gate of said transistor means (25) for a sufficient
period of time to substantially damp switching transients at the source and drain of said transistor
means.
References Cited (Backward Citations)
No citation records indexed.
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