US5233564A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiport memory with test signal generating circuit controlling data transfer from ram port to sam port
Assignee: Toshiba Corp
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Filing: 1991-06-10
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Granted: 1993-08-03
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Expires: 2011-06-10
Abstract
Abstract The disclosed semiconductor memory comprises a random access memory port, a serial access memory port, a data transfer gate formed between the two ports, and in particular a test signal generating circuit for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.
Inventors
- 👤 Shigeo Ohshima
- 👤 Tatsuo Ikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:27
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46; G11C29/003; G11C29/02; G11C7/00; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
126 words
A semiconductor memory, comprising: a random access memory port composed of memory cells arranged on a semiconductor chip in matrix fashion; a serial access memory port composed of serial data registers arranged on the same semiconductor chip in a column direction of said random access memory port; a data transfer gate provided between said random access memory port and the serial access memory port; and test signal generating means for generating a test signal to said data transfer gate to close the gate, when data stored in said serial access memory port are read to outside, whereby the data stored in the serial access memory port can be read to outside, without transferring data from said random access memory port to said serial access memory port.
Claim 2
Dependent Claim
126 words
A semiconductor memory, comprising: a random access memory port composed of memory cells arranged on a semiconductor chip in matrix fashion; a serial access memory port composed of serial data registers arranged on the same semiconductor chip in a column direction of said random access memory port; a data transfer gate provided between said random access memory port and the serial access memory port; and test signal generating means for generating a test signal to said data transfer gate to close the gate, when data stored in said serial access memory port are read to outside, whereby the data stored in the serial access memory port can be read to outside, without transferring data from said random access memory port to said serial access memory port.
Claim 3
Dependent Claim
51 words
The semiconductor memory of claim 1, which further comprises an electrode formed on the semiconductor chip and connected to said test signal generating means, and a lead connected to said electrode, said test signal generating means generating the test signal when a predetermined potential is supplied to the lead from outside.
Claim 4
Dependent Claim
36 words
The semiconductor memory of claim 1, wherein said test signal generating means generates the test signal at timing prescribed by a combination of plural signal levels not defined as ordinary operation modes of said semiconductor memory.
Claim 5
Dependent Claim
28 words
The semiconductor memory of claim 1, wherein said test signal generating means comprises means for inhibiting the test signal from being generated when said semiconductor memory is shipped.
Claim 6
Dependent Claim
37 words
The semiconductor memory of claim 1, wherein said random access memory port, said serial access memory port, and said data transfer gate are divided into a plurality of ports or gates, respectively, to enable split data transfer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |