US5268639A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Testing timing parameters of high speed integrated circuit devices
Assignee: RANBUS Inc
•
Filing: 1992-06-05
•
Granted: 1993-12-07
•
Expires: 2012-06-05
Abstract
Abstract A method and apparatus for testing input and output parameters for high speed integrated circuit devices. An integrated circuit tester generates a receive clock and a transmit clock using a pair of pre-selected output pins. The integrated circuit tester adjusts the phase relation between the transmit clock and the receive clock. Special circuitry within the device under test compares input and output data to detect errors.
Inventors
- 👤 James A. Gasbarro
- 👤 Mark A. Horowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:24
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/022; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31937; G11C29/028; G11C29/04; G11C29/50; G11C29/50012; G01R31/30; G01R31/31903; G01R31/31908; G01R31/3191; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
168 words
A method for testing clock to output time for an integrated circuit device, comprising the steps of: (a) storing an output parameter test pattern in the integrated circuit device; (b) generating a receive clock and a transmit clock using a pair of output pins of an integrated circuit tester; (c) coupling the transmit clock to a transmit clock input of the integrated circuit device, such that the transmit clock causes the integrated circuit device to generate an output data bit stream by transmitting the output parameter test pattern over a bus data pin; (d) coupling the receive clock to a receive clock input of the integrated circuit device, such that the receive clock causes the integrated circuit device to generate an input data pattern by sampling the output data bit stream on the bus data pin; (e) adjusting the phase relation between the transmit clock and the receive clock, and comparing the input data pattern with the output data bit stream to determine the clock to output time.
Claim 2
Independent Claim
168 words
A method for testing clock to output time for an integrated circuit device, comprising the steps of: (a) storing an output parameter test pattern in the integrated circuit device; (b) generating a receive clock and a transmit clock using a pair of output pins of an integrated circuit tester; (c) coupling the transmit clock to a transmit clock input of the integrated circuit device, such that the transmit clock causes the integrated circuit device to generate an output data bit stream by transmitting the output parameter test pattern over a bus data pin; (d) coupling the receive clock to a receive clock input of the integrated circuit device, such that the receive clock causes the integrated circuit device to generate an input data pattern by sampling the output data bit stream on the bus data pin; (e) adjusting the phase relation between the transmit clock and the receive clock, and comparing the input data pattern with the output data bit stream to determine the clock to output time.
Claim 3
Dependent Claim
66 words
The method of claim 1, wherein the pair of output pins of the integrated circuit tester are pre-selected from among a plurality of available output pins of the integrated circuit to maximize an output accuracy between the pair of output pins, the output accuracy specifying an uncertainty in a relative phase difference between the receive clock and the transmit clock on the pair of output pins.
Claim 4
Dependent Claim
48 words
The method of claim 1, wherein step (e) comprises the step of advancing the phase of the receive clock relative to the transmit clock and comparing the input data pattern with the output data bit stream to determine the clock to output time for the integrated circuit device.
Claim 5
Dependent Claim
29 words
The method of claim 1, wherein the output parameter test pattern comprises a set of data bits including a set of drive bits and a set of test bits.
Claim 6
Dependent Claim
37 words
The method of claim 4, wherein the step of comparing the input data pattern with the output data bit stream in step (e) comprises the step of comparing the drive data bits with the test data bits.
References Cited (Backward Citations)
US4247817A
Cited
US4811202A
Cited
US4481625A
Cited
US4519034A
Cited
US4860198A
Cited
US4785394A
Cited
US4893072A
Cited
US4878209A
Cited
US4929888A
Cited
WO1991002590A2
Cited
US5083299A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |