US4893072A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for testing an integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1988-06-22
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Granted: 1990-01-09
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Expires: 2008-06-22
Abstract
Abstract An IC tester for testing an IC device having clocked circuits operative to process a signal under control of a clock signal with a time delay shift comprises a generator for generating a test signal to be supplied to the IC device under control of a timing signal having a repetition period equal to the period of the clock signal, a generator for generating an expected signal to be hopefully delivered from the IC device in response to the test signal, a shifting circuit for effecting a time delay shift of the expected signal equal to the time delay shift in the clocked circuits in the integrated circuit device, and a comparator for comparing the output signal of the IC device responsive to the test signal with the expected signal delivered through the shifting circuit to thereby determine performance characteristics of the IC device.
Inventors
- 👤 Takashi Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31937
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
130 words
An apparatus for testing an integrated circuit device comprising: means for generating a test signal to be supplied to said integrated circuit device under control of a clock signal so that said integrated circuit device produces an output signal in response to said test signal; means for generating an expected signal to be hopefully delivered from said integrated circuit device in response to said test signal; means connected with said expected signal generating means for transferring said expected signal under control of said clock signal with a time delay shift associated with the period of said clock signal; and means for comparing said output signal of said integrated circuit device with said expected signal delivered through said expected signal transferring means to check performance characteristics of said integrated circuit device.
Claim 2
Independent Claim
130 words
An apparatus for testing an integrated circuit device comprising: means for generating a test signal to be supplied to said integrated circuit device under control of a clock signal so that said integrated circuit device produces an output signal in response to said test signal; means for generating an expected signal to be hopefully delivered from said integrated circuit device in response to said test signal; means connected with said expected signal generating means for transferring said expected signal under control of said clock signal with a time delay shift associated with the period of said clock signal; and means for comparing said output signal of said integrated circuit device with said expected signal delivered through said expected signal transferring means to check performance characteristics of said integrated circuit device.
Claim 3
Dependent Claim
85 words
An apparatus according to claim 1, in which said expected signal transferring means includes a plurality of transferring circuits each being arranged so as to be clocked by said clock signal to shift said expected signal by a time identical with the repetition period of said clock signal and a selector circuit for selecting a predetermined number of said clocked transferring circuits so that said expected signal is transferred to said comparing means with a time delay shift determined by the selected clocked transferring circuits.
Claim 4
Dependent Claim
17 words
An apparatus according to claim 2, in which each of said transferring circuits is a flip-flop circuit.
Claim 5
Dependent Claim
17 words
An apparatus according to claim 2, in which each of said transferring circuits is a latch circuit.
Claim 6
Dependent Claim
58 words
An apparatus according to claim 1, further comprising means connected with said test signal generating means for transferring said test signal under control of said clock signal with a time delay shift associated with the period of said clock signal so that said integrated circuit device produces said output signal in response to the so shifted test signal.
Claim 7
Dependent Claim
86 words
An apparatus according to claim 5, in which said test signal transferring means includes a plurality of transferring circuits each being arranged so as to be clocked by said clock signal to shift said test signal by a time identical with the repetition period of said clock signal and a selector circuit for selecting a predetermined number of said clocked transferring circuits so that said test signal is transferred to said integrated circuit device with a time delay shift determined by the selected clocked transferring circuits.
Claim 8
Dependent Claim
17 words
An apparatus according to claim 6, in which each of said transferring circuits is a flip-flop circuit.
Claim 9
Dependent Claim
17 words
An apparatus according to claim 6, in which each of said transferring circuits is a latch circuit.
Claim 10
Independent Claim
249 words
An apparatus for testing a first circuit section in an integrated circuit device fabricated on a single chip, the integrated circuit device further having on the single chip a second circuit section arranged to be clocked with a clock signal, said first circuit section delivering an output signal responsive to an input signal supplied thereto, said second circuit section serving to process at least one of the input signal to and the output signal from said first circuit section under control of said clock signal with a time delay shift associated with the period of said clock signal, the apparatus comprising: means capable of generating said clock signal; means for generating a test signal to be supplied to said first circuit section through said second circuit section in said integrated circuit device under control of said clock signal so that said first circuit section produces an output signal in response to said test signal; means for generating an expected signal to be hopefully delivered from said first circuit section in response to said test signal; means connected with said expected signal generating means for transferring said expected signal under control of said clock signal with a time delay shift associated with the period of said clock signal; and means for comparing said output signal of said first circuit section in said integrated circuit device with said expected signal delivered through said expected signal transferring means to check performance characteristics of said first circuit section in said integrated circuit device.
Claim 11
Independent Claim
249 words
An apparatus for testing a first circuit section in an integrated circuit device fabricated on a single chip, the integrated circuit device further having on the single chip a second circuit section arranged to be clocked with a clock signal, said first circuit section delivering an output signal responsive to an input signal supplied thereto, said second circuit section serving to process at least one of the input signal to and the output signal from said first circuit section under control of said clock signal with a time delay shift associated with the period of said clock signal, the apparatus comprising: means capable of generating said clock signal; means for generating a test signal to be supplied to said first circuit section through said second circuit section in said integrated circuit device under control of said clock signal so that said first circuit section produces an output signal in response to said test signal; means for generating an expected signal to be hopefully delivered from said first circuit section in response to said test signal; means connected with said expected signal generating means for transferring said expected signal under control of said clock signal with a time delay shift associated with the period of said clock signal; and means for comparing said output signal of said first circuit section in said integrated circuit device with said expected signal delivered through said expected signal transferring means to check performance characteristics of said first circuit section in said integrated circuit device.
Claim 12
Dependent Claim
35 words
An apparatus according to claim 9, in which the time delay shift in said expected signal transferring means is equal to the time delay shift in said second circuit section in said integrated circuit device.
Claim 13
Independent Claim
265 words
An apparatus for testing a memory circuit section in an integrated circuit device fabricated on a single chip, the integrated circuit device further having on the single chip a logic circuit section arranged to be clocked with a clock signal, said memory circuit section delivering an output signal responsive to an input signal supplied thereto, said logic circuit section serving to process at least one of the input signal to and the output signal from said memory circuit section under control of said clock signal with a time delay shift associated with the period of said clock signal, the apparatus comprising: means capable of generating said clock signal; means for generating an address signal and an enable signal to be supplied to said memory circuit section through said logic circuit section in said integrated circuit device under control of said clock signal so that said memory circuit section produces an output signal in response to said address and enable signals; means for generating an expected signal to be hopefully delivered from said memory circuit section in response to said address and enable signals; means connected with said expected signal generating means for transferring said expected signal under control of said clock signal with a time delay shift identical with said time delay shift in said logic circuit section in said integrated circuit device; and means for comparing said output signal of said memory circuit section in said integrated circuit device with said expected signal delivered through said expected signal transferring means to check performance characteristics of said memory circuit section in said integrated circuit device.
Claim 14
Independent Claim
265 words
An apparatus for testing a memory circuit section in an integrated circuit device fabricated on a single chip, the integrated circuit device further having on the single chip a logic circuit section arranged to be clocked with a clock signal, said memory circuit section delivering an output signal responsive to an input signal supplied thereto, said logic circuit section serving to process at least one of the input signal to and the output signal from said memory circuit section under control of said clock signal with a time delay shift associated with the period of said clock signal, the apparatus comprising: means capable of generating said clock signal; means for generating an address signal and an enable signal to be supplied to said memory circuit section through said logic circuit section in said integrated circuit device under control of said clock signal so that said memory circuit section produces an output signal in response to said address and enable signals; means for generating an expected signal to be hopefully delivered from said memory circuit section in response to said address and enable signals; means connected with said expected signal generating means for transferring said expected signal under control of said clock signal with a time delay shift identical with said time delay shift in said logic circuit section in said integrated circuit device; and means for comparing said output signal of said memory circuit section in said integrated circuit device with said expected signal delivered through said expected signal transferring means to check performance characteristics of said memory circuit section in said integrated circuit device.
Claim 15
Dependent Claim
56 words
An apparatus according to claim 9, further comprising means connected with said test signal generating means for transferring said test signal under control of said clock signal with a time delay shift associated with the period of said clock signal wherein said first circuit section produces said output signal in response to the shifted test signal.
Claim 16
Dependent Claim
65 words
An apparatus according to claim 11, further comprising means connected with said address signal and enable signal generating means for transferring at least one of said address signal and enable signal under control of said clock signal with a time delay shift associated with the period of said clock signal wherein said memory circuit section produces said output signal in response to the shifted signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-08 | 1993-07-10 | 1994-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-08 | 1997-07-10 | 1998-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-08 | 2001-07-10 | 2002-01-09 | $7700.00 | Window Closed / Lapsed |