Precision phase synchronization of free-running oscillator output signal to reference signal

Claim 2

A circuit for providing a synchronized output signal at a predetermined frequency which is synchronized with a selected transition of an input reference signal, comprising (a) delay means coupled to receive an input signal oscillating at said predetermined frequency for generating a plurality of output signals at said predetermined frequency, each output signal being shifted in phase with respect to the input signal on a different fraction of the period of the input signal, (b) means for selecting that output signal from the delay means having a transition at a time closest to the time of said selected transition of said reference signal, and (c) means for outputting said selected output signal as said synchronized output signal.

Claim 3

A circuit according to claim 1, wherein said delay means comprises means for producing a plurality of delayed output signals each incrementally displaced an interval of time equal to aP/b, where b is the number of plurality of output signals, a is an integer between 0 and b and P is the periodicity of the input signal.

Claim 4

A circuit according to claim 2, wherein said delay means includes means for producing said plurality of output signals each of which alternates between a first and second value, and wherein said selecting means comprises (i) store and hold means for selecting the value of each output signal at a time corresponding to said selected transition, (ii) means for comparing each value of adjacent incrementally delayed output signals and for providing a plurality of associated signals each indicative of whether the compared values are the same or are dissimilar, (iii) means responsive to said associated signals for outputting a control signal indicative of the first associated signal corresponding to adjacent delayed output signals having dissimilar values at the time of said selected transition, and (iv) means responsive to said control signal for outputting the first delayed output signal which resulted in said first associated signal as said synchronized output signal.

Claim 5

A circuit according to claim 3, wherein said comparing means produces binary associated signals having a first state if the stored values of adjacent delayed output signals are the same at the time of said selected transition and having a second state if the stored values of adjacent delayed output signals are dissimilar at the time of said selected transition, and wherein said control signal outputting means includes means for comparing the states of the adjacent associated signals and for providing a binary coded control signal indicative of said first associated signal.

Claim 6

A circuit according to claim 1, wherein (a) said delay means is coupled to receive an input signal and includes means for generating a plurality of output signals at the same frequency as the input signal, each of which is shifted in phase a fraction of the period thereof, (b) said selecting means includes means responsive to the phase shift between the input signal and each output signal at the time of said selected transition, and (c) means for selectively operating on the output signals to cause the selected output signal to have a transition in phase with the selected transition of the reference signal.