Flip-flop circuit

Claim 2

A flip-flop circuit comprising: driving gate means for receiving a pair of complementary data signals and outputting a single phase data signal indicative of said complementary data signals; and memory means, connected to a first output node of said driving gate means, for holding the output signal of said driving gate means and outputting a pair of complementary signals indicative of said pair of complementary data signals, respectively, wherein said driving gate means includes a first tri-state gate having inputs for receiving said pair of complementary data signals and responding thereto, in response to a clock signal, for providing said single phase data signal to said first output node, and wherein said first tri-state gate comprises: a first NOR gate for receiving at a first input thereof a first one of said pair of complementary data signals and at a second input thereof said clock signal, a second NOR gate for receiving at a first input thereof the second one of said pair of complementary data signals and at a second input thereof said clock signal, a first normally-off type FET, a gate of which is connected to an output of said first NOR gate and a drain of which is connected to a first power source terminal, and a second normally-off type FET, a gate of which is connected to an output of said second NOR gate, a drain of which is commonly connected with a source of said first normally-off type FET to said first output node of said driving gate means and a source of which is connected to a second power source terminal.

Claim 3

A flip-flop circuit according to claim 1, wherein said driving gate means further includes a second tri-state gate having inputs for receiving said pair of complementary data signals and, responsive to said clock signal, for providing at a second output node of said driving gate means, connected with said memory means, a complementary signal to that provided-by said first tri-state gate; and which said second tri-state gate includes: a third NOR gate for receiving at a first input thereof the second one of said pair of complementary data signals and at a second input thereof said clock signal, a fourth NOR gate for receiving at a first input thereof the first one of said pair of complementary data signals and at a second input thereof said clock signal, a third normally-off type FET, a gate of which is connected to an output of the third NOR gate and a drain of which is connected to said first power source terminal, and a fourth normally-off type FET, a gate of which is connected to an output of said fourth NOR gate, a drain of which is commonly connected with a source of said third normally-off type FET to said second output node of said driving gate means and a source of which is connected to said second power source terminal.

Claim 4

A flip-flop circuit according to claim 2, wherein said memory means includes a pair of cross-coupled inverters, a first one of said pair of inverters has an input and output connected between said second output node and said first output node of said gate driving means, respectively, and the second of said pair of inverters has an input and output connected between said first output node and said second output node of said gate driving means, respectively.

Claim 5

A flip-flop circuit according to claim 3, wherein said first and second power source terminals correspond to positive and negative power source terminals, respectively.

Claim 6

A flip-flop circuit according to claim 3, wherein each inverter of said pair of cross-coupled inverters is a non-clocked inverter.

Claim 7

A flip-flop circuit according to claim 2, wherein each of the respective first and third NOR gates includes: a fifth normally-off type FET, a gate of which receives the first or second one of said pair of complementary data signals, a source of which is connected to said second power source terminal, and a drain of which is connected to the output of said first or third NOR gate; a sixth normally-off type FET, a gate of which receives said clock signal, a source of which is connected to said second power source terminal, and a drain of which is commonly connected to the drain of said fifth normally-off type FET and the output of said first or third NOR gate; a first normally-on type FET, a drain of which is connected to said first power source terminal and a source of which is connected to the output of said first or third NOR gate; and wherein each of the respective second and fourth NOR gates includes: a seventh normally-off type FET, a gate of which receives the second or first one of said pair of complementary data signals, a source of which is connected to said second power source terminal, and a drain of which is connected to the output of said second or fourth NOR gate; an eighth normally-off type FET, a gate of which receives said clock signal, a source of which is connected to said second power source terminal, and a drain of which is commonly connected to the drain of said seventh normally-off type FET and the output of said second or fourth NOR gate; and a second normally-on type FET, a drain of which is connected to said first power source terminal, and a source of which is connected to the output of said second or fourth NOR gate.

Claim 8

A flip-flop circuit according to claim 6, wherein the gate of said first normally-on type FET is coupled to receive a fixed voltage source.

Claim 9

A flip-flop circuit according to claim 7, wherein each of said first and third NOR gates includes a clamp circuit connected between the output of the respective one of said first and third NOR gates and said second power source terminal.

Claim 10

A flip-flop circuit according to claim 8, wherein said clamp circuit includes a normally-off type FET, a drain of which is connected to the output of said first or third NOR gate, a source of which is connected to said second power source terminal, and a gate of which is connected to an output of said first or second tri-state gate and which output corresponds to one of said first and second output nodes of said driving gate means, respectively.

Claim 11

A flip-flop circuit according to claim 9, wherein said first and second power source terminals correspond to positive and negative power source terminals, respectively.

Claim 12

A flip-flop circuit according to claim 1, wherein said memory means includes an inverter having an input coupled to said first output node to receive the single phase data output signal of said driving gate means and in response thereto outputting an inverter signal thereof, a second tri-state gate having inputs coupled to receive the inverted signal of said inverter and the output signal of said driving gate means, respectively, and having an output coupled to said first output node, whereby holding of the output signal of said driving gate means is effected in response to a control provided by said clock signal and a phase complement clock signal thereof.

Claim 13

A flip-flop circuit according to claim 11, wherein said second tri-state gate includes: a third NOR gate for receiving at first and second inputs thereof the output signal of said inverter and said phase complement clock signal, respectively; a fourth NOR gate for receiving at first and second inputs thereof the output signal of said driving gate means and said phase complement clock signal; a third normally-off type FET, a gate of which is connected to an output of said third NOR gate and a drain of which is connected to said first power source terminal; and a fourth normally-off type FET, a gate of which is connected to an output node of said fourth NOR gate, a drain of which is commonly connected with the source of said third normally-off type FET to said first output node of said driving gate means, and a source of which is connected to said second power source terminal.

Claim 14

A flip-flop circuit according to claim 12, wherein each of said first, second, third and fourth NOR gates includes: a first normally-on type FET, a drain of which is connected to said first power source terminal and a source of which is connected to the output node of said first, second third or fourth NOR gate, respectively; a fifth normally-off type FET, a gate of which is connected to one input node of said first, second, third or fourth NOR gate, a drain of which is connected to the source of said first normally-on type FET, and a source of which is connected to said second power source terminal, respectively; and a sixth normally-off type FET, a gate of which is connected to another input node of said first, second, third and fourth NOR gate, a drain of which is connected to the source of said first normally-on type FET, and a source of which is connected to said second power source terminal, respectively.

Claim 15

A flip-flop circuit according to claim 13, wherein the gate of said first normally-on type FET is coupled to receive a predetermined fixed voltage source.

Claim 16

A flip-flop circuit according to claim 13, wherein each of said first and third NOR gates includes a clamp circuit connected between the outputs thereof and said second power source terminal, respectively.

Claim 17

A flip-flop circuit according to claim 15, wherein the clamp circuit includes a normally-off type FET, a drain of which is connected to the output of said first or third NOR gate, a source of which is connected to said second power source terminal, and a gate of which is connected to an output of said first or second tri-state gate.

Claim 18

A flip-flop circuit according to claim 16, wherein said first and second power source terminals correspond to positive and negative power source terminals, respectively.

Claim 19

A flip-flop circuit according to claim 1, wherein said first and second power source terminals correspond to positive and negative power source terminals, respectively.

Claim 20

A flip-flop circuit according to claim 18, wherein a voltage potential of about 1 volt is applied to said first power source terminal and 0 volt is applied to said second power source terminal.

Claim 21

A flip-flop circuit according to claim 1, further comprising a second driving gate means coupled to receive the pair of complementary signals outputted from said memory means and providing a second single phase output signal at a second output node of a level indicative of said pair of complementary signals received from said memory means, wherein said second driving gate means includes a second tri-state having inputs for receiving the pair of complementary signals from said memory means and outputting said second single phase signal in response to a phase complement of said clock signal; and a second memory means, connected to said second output node of said second driving gate means holding a previously attained said second output signal at said second output node when said second tri-state gate is in a high impedance state and outputting a pair of complementary data signals.

Claim 22

A flip-flop circuit according to claim 20, wherein said first and second power source terminals correspond to positive and negative power source terminals, respectively.

Claim 23

A flip-flop circuit comprising: driving gate means for receiving a pair of complementary data signals and outputting a single phase data signal indicative of said complementary data signals, wherein said driving gate means includes a first tri-state gate having inputs for receiving said pair of complementary data signals and responding thereto, in response to a clock signal, for providing said single phase data signal to said first output node; memory means, connected to a first node of said driving gate means, for holding the output signal of said driving gate means and outputting a pair of complementary signals indicative of said pair of complementary data signals, respectively; a second driving gate means coupled to receive the pair of complementary signals outputted from said memory means and providing a second single phase output signal at a second output node of a level indicative to the pair of complementary signals received from said memory means wherein said second driving gate means includes a second tri-state gate having inputs for receiving the pair of complementary signals from said memory means and outputting said second single phase signal in response to a phase complement of said clock signal; and a second memory means, connected to said second output node of said second driving gate means, holding a previously attained said second output signal at said second output node when said second tri-state is in a high impedance state and outputting a pair of complementary signals corresponding to said pair of complementary data signals.

Claim 24

A flip-flop circuit comprising: driving gate means for receiving a pair of complementary data signals and outputting a single phase data signal indicative of said complementary data signals, wherein said driving gate means includes a first tri-state gate having inputs for receiving said pair of complementary data signals and responding thereto, in response to a clock signal, for providing said single phase data signal to said first output node; memory means, connected to a first node of said driving gate means, for holding the output signal of said driving gate means and outputting a pair of complementary signals indicative of said pair of complementary data signals, respectively; a second driving gate means coupled to receive the pair of complementary signals outputted from said memory means and providing a second single phase output signal at a second output node of a level indicative to the pair of complementary signals received from said memory means wherein said second driving gate means includes a second tri-state gate having inputs for receiving the pair of complementary signals from said memory means and outputting said second single phase signal in response to a phase complement of said clock signal; and a second memory means, connected to said second output node of said second driving gate means, holding a previously attained said second output signal at said second output node when said second tri-state is in a high impedance state and outputting a pair of complementary signals corresponding to said pair of complementary data signals.

Claim 25

A flip-flop circuit according to claim 22, wherein said first and second power source terminals correspond to positive and negative power source terminals, respectively.

Claim 26

A flip-flop circuit according to claim 20, wherein said phase complement signal of said clock signal is a delayed phase complement clock signal of said clock signal.

Claim 27

A flip-flop circuit comprising: a pair of input terminals for inputting a pair of complementary signals; first and second output terminals for outputting complementary signals corresponding to the pair of complementary input signals; first, second, third and fourth NOR gates, each having first and second inputs and an output, wherein the first of said first and fourth NOR gates are coupled to receive a clock signal and the second inputs of which are connected to one input terminal of said pair of input terminals, respectively, and wherein the first inputs of said second and third NOR gates are coupled to receive said clock signal and the second inputs of which are connected to the other input terminal of said pair of input terminals; a first FET, a gate of which is connected to an output node of the first NOR gate, a drain of which is connected to a first power source terminal, and a source of which is connected to said first output terminal; a second FET, a gate of which is connected to an output node of said second NOR gate, a drain of which is connected to said first output terminal, and a source of which is connected to a second power source terminal; a third FET, a gate of which is connected to an output node of said third NOR gate, a drain of which is connected to said first power source terminal, and a source of which is connected to said second output terminal; a fourth FET, a gate of which is connected to an output node of said fourth NOR gate, a drain of which is connected to said second output terminal; and a pair of inverters, a first one of which has an input and output connected to said first and second output terminals, respectively, and the second one of which has an input and output connected to said second and first output terminals, respectively.

Claim 28

A flip-flop circuit comprising: a pair of input terminals for inputting a pair of complementary signals; first and second output terminals for outputting complementary signals corresponding to the pair of complementary input signals; first, second, third and fourth NOR gates, each having first and second inputs and an output, wherein the first of said first and fourth NOR gates are coupled to receive a clock signal and the second inputs of which are connected to one input terminal of said pair of input terminals, respectively, and wherein the first inputs of said second and third NOR gates are coupled to receive said clock signal and the second inputs of which are connected to the other input terminal of said pair of input terminals; a first FET, a gate of which is connected to an output node of the first NOR gate, a drain of which is connected to a first power source terminal, and a source of which is connected to said first output terminal; a second FET, a gate of which is connected to an output node of said second NOR gate, a drain of which is connected to said first output terminal, and a source of which is connected to a second power source terminal; a third FET, a gate of which is connected to an output node of said third NOR gate, a drain of which is connected to said first power source terminal, and a source of which is connected to said second output terminal; a fourth FET, a gate of which is connected to an output node of said fourth NOR gate, a drain of which is connected to said second output terminal; and a pair of inverters, a first one of which has an input and output connected to said first and second output terminals, respectively, and the second one of which has an input and output connected to said second and first output terminals, respectively.

Claim 29

A flip-flop circuit according to claim 25, wherein said first and second power source terminals correspond to positive and negative power source terminals, respectively.

Claim 30

A flip-flop circuit according to claim 25, wherein a voltage potential of about 1 volt is applied to said first power source terminal and 0 volt is applied to said second power source terminal.

Claim 31

A flip-flop circuit according to claim 25, wherein each inverter of said pair of inverters is a non-clocked inverter.

Claim 32

A flip-flop circuit comprising: a first tri-state gate having inputs for receiving a pair of complementary data signals and, in response to a first clock signal, providing a single phase output signal indicative of said complementary data signals; an inverter having an input coupled to receive the output signal of said first tri-state gate and having an output for providing a phase complement signal of said output signal; and a second tri-state gate, an output node of which is connected to an output node of said first tri-state gate and inputs of which are coupled to receive the output signal of said first tri-state gate and the phase complement output signal from said inverter, for outputting a signal to hold an output voltage of said first tri-state gate in response to a second clock signal, complementary to said first clock signal.

Claim 33

A flip-flop circuit comprising: a first tri-state gate having inputs for receiving a pair of complementary data signals and, in response to a first clock signal, providing a single phase output signal indicative of said complementary data signals; an inverter having an input coupled to receive the output signal of said first tri-state gate and having an output for providing a phase complement signal of said output signal; and a second tri-state gate, an output node of which is connected to an output node of said first tri-state gate and inputs of which are coupled to receive the output signal of said first tri-state gate and the phase complement output signal from said inverter, for outputting a signal to hold an output voltage of said first tri-state gate in response to a second clock signal, complementary to said first clock signal.

Claim 34

A flip-flop circuit according to claim 29, wherein said second clock signal is a delayed phase complement clock signal of said first clock signal.