Memory cell and array

Claim 2

The combination comprising: first and second inverters, each inverter having an input and an output, the inverters being characterized in that they both have a high input impedance and the output impedance of the second inverter being significantly less than the output impedance of the first inverter for the same turn on bias condition; a common input-output point; means cross-coupling the two inverters for forming a flip-flop including means connecting the output of the first inverter to the input of the second inverter, and negligible impedance means connecting the input of the first inverter and the output of the second inverter to said input-output point; and input means connected to said input-output point for selectively setting said flip-flop and for selectively sensing the state of said flip-flop.

Claim 3

The combination as claimed in claim 1 wherein said input means includes: a) a single input-output line adapted to receive signals to be applied to said input-output point or to receive signals from said input-output point; b) a gating transistor having a conduction path and a control electrode, said conduction path being connected between said input-output point and said input-output line; and c) gating control means connected to the control electrode of said gating transistor for turning off said gating transistor relatively quickly and for turning it on relatively slowly.

Claim 4

The combination as claimed in claim 2 wherein each one of said first and second inverters includes first and second transistors each transistor having first and second electrodes defining the ends of a conduction path and a control electrode; wherein the control electrodes of the first and second transistors of an inverter are connected to the input of that inverter, wherein the first electrode of the first transistor of each inverter is connected to a first point of operating potential, wherein the first electrode of the second transistor of each inverter is connected to a second point of operating potential and wherein the second electrodes of the first and second transistors of each inverter are connected to the output of that inverter; and wherein the impedances of the conduction channels of the transistors of the first inverter are greater than the impedances of the conduction channels of the devices of the second inverter for the same value of turn on signal.

Claim 5

The combination as claimed in claim 3 wherein each one of said transistors is an insulated-gate field-effect transistor having a gate electrode and source and drain electrodes defining the ends of a conduction path; wherein said control electrode of each transistor is said gate electrode, each one of said first electrodes is a source electrode, and each one of said second electrodes is a drain electrode; and wherein the first transistors of each one of said inverters is of one conductivity type and wherein the second transistors of each one of said inverters is of another, second conductivity type.

Claim 6

The combination as claimed in claim 4 wherein the time constant to charge or discharge the output of said first inverter is greater than the time constant to change or discharge said input-output point, or said input-output line by means of said second inverter.

Claim 7

The combination as claimed in claim 2 wherein said gating control means includes first and second control transistors each having a control electrode and a conduction path; conduction paths of said first and second control transistors being relatively low; and wherein the conduction path of the first control transistor is connected between a first point of potential and the control electrode of said gating transistor for turning it off; and wherein the conduction path of said second control transistor is connected between a second point of potential and the control electrode of said gating transistor for turning it on.

Claim 8

The combination as claimed in claim 6 wherein said gating control means further includes means applied to the control electrodes of said first and second control transistors for turning said second control transistor on more slowly than said first control transistor.

Claim 9

The combination as claimed in claim 2 further including means for sensing on said input-output line the signal received from said input-output point comprising a sensing inverter having an input connected to said input-output line and an output connected to a data output line; and a semiconductor device having a control electrode connected to the output of said sensing inverter and having a conduction path of relatively high impedance connected between a point of potential and said input-output line for providing regenerative feedback between the output and the input of said sensing inverter for only one signal condition.

Claim 10

The combination as claimed in claim 8 wherein said regenerative feedback device is an insulated-gate field-effect transistor of complementary conductivity type to the conductivity of the gating transistor; and wherein the impedance of the conduction path of said feedback transistor is much greater than that of said gating transistor for the same value of forward bias.

Claim 11

The combination comprising a flip flop having an output point and a single gating transistor having its conduction path connected between said output point and a single sense line, and wherein for one value of stored data said gating transistor conducts in the follower mode whereby the value of the signal read out on said sense line is offset; a high input impedance inverter having an input and an output and first and second power terminals for the application therebetween of an operating potential; said input being connected to said sense line, and said output being connected to a data output line; and a feedback transistor of different conductivity type than said gating transistor having first and second electrodes defining the ends of its conduction path and a control electrode; said control electrode being connected to said data output line, one end of said conduction path being connected to said sense line and the other end of said conduction path being connected to that one of said first and second power terminals having a value to reduce said offset, whereby said feedback transistor, when turned on, reduces said offset.

Claim 12

The combination comprising a flip flop having an output point and a single gating transistor having its conduction path connected between said output point and a single sense line, and wherein for one value of stored data said gating transistor conducts in the follower mode whereby the value of the signal read out on said sense line is offset; a high input impedance inverter having an input and an output and first and second power terminals for the application therebetween of an operating potential; said input being connected to said sense line, and said output being connected to a data output line; and a feedback transistor of different conductivity type than said gating transistor having first and second electrodes defining the ends of its conduction path and a control electrode; said control electrode being connected to said data output line, one end of said conduction path being connected to said sense line and the other end of said conduction path being connected to that one of said first and second power terminals having a value to reduce said offset, whereby said feedback transistor, when turned on, reduces said offset.

Claim 13

The combination as claimed in claim 10 wherein said inverter is a complementary inverter having a first transistor of one conductivity type and a second transistor of second conductivity type; wherein said gating transistor is of one conductivity type and said feedback is of second conductivity type; and wherein said other end of said conduction path of said feedback transistor is connected to the same power terminal as said second transistor.

Claim 14

The combination as claimed in claim 11 wherein the impedance of the conduction path of said feedback transistor is significantly greater than that of said gating and first and second transistors for the same value of forward bias.