High speed MOSFET output buffer with low noise

Claim 2

A semiconductor integrated circuit comprising: (1) a data output terminal; (2) a first semiconductor element having a control input terminal, whose output current path is connected between a first operating potential point and said data output terminal; (3) a second semiconductor element having a control input terminal, whose output current path is connected between said data output terminal and a second operating potential point; (4) a first controller connected to said control input terminal of said first semiconductor element; (5) a second controller connected to said control input terminal of said second semiconductor element; (6) a first generator for generating a first predetermined voltage; and (7) a second generator for generating a second predetermined voltage, which is higher than said first predetermined voltage, wherein the voltage of said first operating potential is higher than said second predetermined voltage, and the voltage of said second operating potential is lower than said first predetermined voltage, wherein in the case where the voltage of said data output terminal is higher than that of said second predetermined voltage, the output of said first controller controls said control input of said first semiconductor element so that the current flowing through said output current path of said first semiconductor element is substantially zero and the output of said second controller controls said control input of said second semiconductor element so that a second predetermined current flows through said output current path of said second semiconductor element, so as to lower said voltage of said data output terminal to a voltage, which is substantially equal to said second predetermined voltage, and wherein in the case where the voltage of said data output terminal is lower than that of said first predetermined voltage, the output of said first controller controls said control input of said first semiconductor element so that a first predetermined current flows through said output current path of said first semiconductor element and the output of said second controller controls said control input of said second semiconductor element so that the current flowing through said output current path of said second semiconductor element is substantially zero, so as to raise said voltage of said data output terminal to a voltage, which is substantially equal to said first predetermined voltage.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein said first controller carries out a voltage comparison, by which the voltage of said data output terminal and said first predetermined voltage are compared with each other; and wherein said second controller carries out a voltage comparison, by which the voltage of said data output terminal and said second predetermined voltage are compared with each other.

Claim 4

A semiconductor integrated circuit according to claim 2, further comprising: (8) a first gate circuit for transmitting a first signal to said control input terminal of said first semiconductor element; (9) a second gate circuit for transmitting the output of said first controller to said control input terminal of said first semiconductor element; (10) a third gate circuit for transmitting the output of said second controller to said control input terminal of said second semiconductor element; and (11) a fourth gate circuit for transmitting a second signal, which is opposite in phase to said first signal, to said control input terminal of said second semiconductor element.

Claim 5

A semiconductor integrated circuit according to claim 3, wherein said first and said second signals are complementary signals read-out from a memory cell in the semiconductor integrated circuit.

Claim 6

A semiconductor integrated circuit according to claim 4, further comprising: (12) address selection circuits for accessing said memory in said semiconductor integrated circuit, responding to an address signal; and (13) an address transition detector for generating a control pulse having a predetermined level during a predetermined period of time, responding to changes of said address signal; wherein said predetermined level of said control pulse allows the signal transmission of said second and said third gate circuit and prohibits the signal transmission of said first and said fourth gate circuits.

Claim 7

A semiconductor integrated circuit comprising: (1) a data output terminal; (2) a first semiconductor element having a control input terminal, whose output current path is connected between a first operating potential point and said data output terminal; (3) a second semiconductor element having a control input terminal, whose output current path is connected between said data output terminal and a second operating potential point; (4) a first controller connected to said control input terminal of said first semiconductor element; (5) a second controller connected to said control input terminal of said second semiconductor element; (6) a first generator for generating a first predetermined voltage; and (7) a second generator for generating a second predetermined voltage, which is higher than said first predetermined voltage, wherein in the case where the voltage of said data output terminal is higher than that of said second predetermined voltage, the output of said first controller controls said control input of said semiconductor element so that the current flowing through said output current path of said first semiconductor element is substantially zero and the output of said second controller controls said control input of said second semiconductor element so that a second predetermined current flows through said output current path of said second semiconductor element, so as to lower said voltage of said data output terminal to a voltage, which is substantially equal to said second predetermined voltage, wherein in the case where the voltage of said data output terminal is lower than that of said first predetermined voltage, the output of said first controller controls said control input of said first semiconductor element so that a first predetermined current flows through said output current path of said first semiconductor element and the output of said second controller controls said control input of said second semiconductor element so that the current flowing through said output current path of said second semiconductor element is substantially zero, so as to raise said voltage of said data output terminal to a voltage, which is substantially equal to said first predetermined voltage, wherein said first controller carries out a voltage comparison, by which the voltage of said data output terminal and said first predetermined voltage are compared with each other, and wherein said second controller carries out a voltage comparison, by which the voltage of said data output terminal and said second predetermined voltage are compared with each other.

Claim 8

A semiconductor integrated circuit comprising: (1) a data output terminal; (2) a first semiconductor element having a control input terminal, whose output current path is connected between a first operating potential point and said data output terminal; (3) a second semiconductor element having a control input terminal, whose output current path is connected between said data output terminal and a second operating potential point; (4) a first controller connected to said control input terminal of said first semiconductor element; (5) a second controller connected to said control input terminal of said second semiconductor element; (6) a first generator for generating a first predetermined voltage; and (7) a second generator for generating a second predetermined voltage, which is higher than said first predetermined voltage, wherein in the case where the voltage of said data output terminal is higher than that of said second predetermined voltage, the output of said first controller controls said control input of said semiconductor element so that the current flowing through said output current path of said first semiconductor element is substantially zero and the output of said second controller controls said control input of said second semiconductor element so that a second predetermined current flows through said output current path of said second semiconductor element, so as to lower said voltage of said data output terminal to a voltage, which is substantially equal to said second predetermined voltage, wherein in the case where the voltage of said data output terminal is lower than that of said first predetermined voltage, the output of said first controller controls said control input of said first semiconductor element so that a first predetermined current flows through said output current path of said first semiconductor element and the output of said second controller controls said control input of said second semiconductor element so that the current flowing through said output current path of said second semiconductor element is substantially zero, so as to raise said voltage of said data output terminal to a voltage, which is substantially equal to said first predetermined voltage, wherein said first controller carries out a voltage comparison, by which the voltage of said data output terminal and said first predetermined voltage are compared with each other, and wherein said second controller carries out a voltage comparison, by which the voltage of said data output terminal and said second predetermined voltage are compared with each other.

Claim 9

A semiconductor integrated circuit according to claim 6, further comprising: (8) a first gate circuit for transmitting a first signal to said control input terminal of said first semiconductor element; (9) a second gate circuit for transmitting the output of said first controller to said control input terminal of said first semiconductor element; (10) a third gate circuit for transmitting the output of said second controller to said control input terminal of said second semiconductor element; and (11) a fourth gate circuit for transmitting a second signal, which is opposite in phase to said first signal, to said control input terminal of said second semiconductor element.

Claim 10

A semiconductor integrated circuit according to claim 7, wherein said first and said second signals are complementary signals read-out from a memory cell in the semiconductor integrated circuit.

Claim 11

A semiconductor integrated circuit according to claim 8, further comprising: (12) address selection circuits for accessing said memory in said semiconductor integrated circuit, responding to an address signal; and (13) an address transition detector for generating a control pulse having a predetermined level during a predetermined period of time, responding to changes of said address signal, wherein said predetermined level of said control pulse allows the signal transmission of said second and said third gate circuit and prohibits the signal transmission of said first and said fourth gate circuits.