US5283631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1991-11-01
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Granted: 1994-02-01
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Expires: 2011-11-01
Abstract
Abstract A delay element for fine tuning the position in time of timing edges of an input signal, comprising a first and a second inventer, each comprising a data input, a control input and a data output. The delay element further comprises a node comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage is included for applying a biasing voltage to the first and second control inputs to thereby control the amount of charge supplied to the node. Finally, the variable capacitance means is connected to the node for applying finite amounts of capacitance to the node to delay and thereby fine tune in time the timing edges of the input signal propagating from the first inverter to the second inverter.
Inventors
- 👤 Christopher Koerner
- 👤 Alberto Gutierrez, Jr.
- 👤 Edward G. Pumphrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:03
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2832; G01R31/2836; G01R31/2839; G01R31/2841; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; H03K5/133; H03M; H03M1/00; H03M1/66; H03M1/68; H03M1/687; H03K2005/00013; H03K2005/00078; H03K2005/00097; H03M1/74; H03M1/742; H03M1/745; H03M1/747
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
129 words
A pseudo-NMOS inverter comprising: (a) a first field effect transistor (FET) having first gate, source, and drain electrodes; (b) an second FET having second gate, source, and drain electrodes, said second gate electrode forming an input to the inverter, and said second drain electrode being connected to said first drain electrode to thereby form an output node of the inverter; (c) means for connecting a voltage supply to said first source and said second source electrodes; and (d) means for applying an adjustable control voltage to said first gate electrode to thereby determine the conductivity of said first FET, said adjustable control voltage substantially offsets temperature and voltage supply variations, wherein changing said adjustable voltage regulates the amount of current flowing from the voltage supply to said output node.
Claim 2
Dependent Claim
129 words
A pseudo-NMOS inverter comprising: (a) a first field effect transistor (FET) having first gate, source, and drain electrodes; (b) an second FET having second gate, source, and drain electrodes, said second gate electrode forming an input to the inverter, and said second drain electrode being connected to said first drain electrode to thereby form an output node of the inverter; (c) means for connecting a voltage supply to said first source and said second source electrodes; and (d) means for applying an adjustable control voltage to said first gate electrode to thereby determine the conductivity of said first FET, said adjustable control voltage substantially offsets temperature and voltage supply variations, wherein changing said adjustable voltage regulates the amount of current flowing from the voltage supply to said output node.
Claim 3
Dependent Claim
154 words
A delay element for fine tuning the position in time of timing edges of an input signal, comprising: (a) a first and a second inverter, each comprising a data input, a control input, a data output, and connections for applying a voltage supply to said inverters; (b) a node defining a connection between said data output of said first inverter and said data input of said second inverter; (c) an adjustable control voltage for applying a biasing voltage to said first and second control inputs to thereby control the amount of charge supplied to said node by the voltage supply, said adjustable control voltage substantially offsets temperature and voltage supply variations; and (d) a variable capacitance means connected to said node for applying finite amounts of capacitance to said node to delay and thereby fine tune in time the timing edges of the input signal propagating from said first inverter to said second inverter.
Claim 4
Dependent Claim
154 words
A delay element for fine tuning the position in time of timing edges of an input signal, comprising: (a) a first and a second inverter, each comprising a data input, a control input, a data output, and connections for applying a voltage supply to said inverters; (b) a node defining a connection between said data output of said first inverter and said data input of said second inverter; (c) an adjustable control voltage for applying a biasing voltage to said first and second control inputs to thereby control the amount of charge supplied to said node by the voltage supply, said adjustable control voltage substantially offsets temperature and voltage supply variations; and (d) a variable capacitance means connected to said node for applying finite amounts of capacitance to said node to delay and thereby fine tune in time the timing edges of the input signal propagating from said first inverter to said second inverter.
Claim 5
Dependent Claim
186 words
A delay element for fine tuning the position in time of timing edges of an input signal, comprising: (a) a first and a second inverter, each comprising a data input, a control input, and a data output; (b) a node defining a connection between said data output of said first inverter and said data input of said second inverter; (c) an adjustable control voltage for applying a biasing voltage to said first and second control inputs to thereby control the amount of charge supplied to said node; and (d) a variable capacitance means connected to said node for applying finite amounts of capacitance to said node to delay and thereby fine tune in time the timing edges of the input signal propagating from said first inverter to said second inverter, said variable capacitance having: (i) decoder means for decoding an input control word and generating at least one control signal; and (ii) at least one capacitor bank coupled to said decoder means and to said node for applying said finite amounts of capacitance to said node as a function of said at least one control signal.
Claim 6
Dependent Claim
186 words
A delay element for fine tuning the position in time of timing edges of an input signal, comprising: (a) a first and a second inverter, each comprising a data input, a control input, and a data output; (b) a node defining a connection between said data output of said first inverter and said data input of said second inverter; (c) an adjustable control voltage for applying a biasing voltage to said first and second control inputs to thereby control the amount of charge supplied to said node; and (d) a variable capacitance means connected to said node for applying finite amounts of capacitance to said node to delay and thereby fine tune in time the timing edges of the input signal propagating from said first inverter to said second inverter, said variable capacitance having: (i) decoder means for decoding an input control word and generating at least one control signal; and (ii) at least one capacitor bank coupled to said decoder means and to said node for applying said finite amounts of capacitance to said node as a function of said at least one control signal.
Claim 7
Dependent Claim
26 words
A delay element according to claim 3, wherein said decoder means comprises a plurality of bits to thereby provide programmability of at least one capacitor bank.
Claim 8
Dependent Claim
135 words
A delay element according to claim 2, wherein said first and second inverters each comprises: (a) a first Field Effect Transistor (FET) having first gate, source, and drain electrodes; (b) a second FET having second gate, source, and drain electrodes, said second gate electrode forming an input to the respective inverter, and said second drain electrode being connected to said first drain electrode to thereby form an output node of the respective inverter; (c) means for permitting a voltage supply to be connected to said first source and said second source electrodes; and (d) means for applying an adjustable control voltage to said first gate electrode to thereby determine the conductivity of said first FET, wherein changing said adjustable control voltage regulates the amount of current flowing from the voltage supply to said output node.
Claim 9
Dependent Claim
36 words
A delay element according to claim 5, wherein said first FET is a p-channel FET and said second FET is an n-channel FET and the combination of said p-channel and n-channel FETs forms a pseudo-NMOS inverter.
Claim 10
Dependent Claim
15 words
A delay element according to claim 6 which is utilized for delaying negative timing edges.
Claim 11
Dependent Claim
36 words
A delay element according to claim 5, wherein said first FET is an n-channel FET and said second FET is a p-channel FET and the combination of said n-channel and p-channel FETs forms a pseudo-PMOS inverter.
Claim 12
Dependent Claim
15 words
A delay element according to claim 8 which is utilized for delaying positive timing edges.
Claim 13
Dependent Claim
61 words
A delay element according to claim 3, wherein said at least one capacitor bank comprises at least one FET having gate, source and drain electrodes, said gate electrode being coupled to said node and said source and drain electrodes being coupled together and coupled to said decoder means to thereby form a FET capacitor to provide said finite amount of capacitance.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-31 | 1997-08-02 | 1998-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-31 | 2001-08-02 | 2002-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-31 | 2005-08-02 | 2006-02-01 | $7700.00 | Window Closed / Lapsed |