Memory clock pulse generating circuit with reduced peak current requirements

Claim 1

A clock pulse generating circuit comprising: input means for receiving a pulse signal; a plurality of cascade-connected delay circuits each having an input terminal and and an output terminal, a first one of said delay circuits being connected to said input means to receive the pulse signal, and each of said delay circuits delaying an input signal supplied thereto by a fixed delay amount without changing the waveshape of the input signal; at least one delay element selectively connected to at least one output terminal of said delay circuits and whose delay amount is variable; and a control circuit for selectively supplying first and second control signals to said at least one delay element so as to change the delay amount of said at least one delay element; said delay element comprising a MOS transistor having a gate connected to said control circuit and a current path connected at one end to the output and input terminals of corresponding first and second delay circuits, respectively, said delay element further comprising a capacitive element connected between the other end of the current path of said MOS transistor and a reference potential terminal, said MOS transistor being rendered nonconductive in response to said second control signal.