Delay line using integrated mos circuitry

Claim 2

Analog signal delay apparatus of the ''''bucket brigade'''' type comprising, in combination: a plurality of delay stages in cascade, each of said delay stages including: a. a delay stage input terminal; b. a delay stage output terminal; c. a first MOS transistor amplifier of substantially unity gain having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; d. a first MOS switching transistor having gate, source and drain electrodes, the source-drain path of said first MOS switching transistor being disposed serially between said delay stage input terminal and said input electrode of said first MOS transistor amplifier, said first switching transistor providing, when rendered conducting, a low impedance conductive path between said delay stage input terminal and said input electrode of said first transistor amplifier for altering the charge on said storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said delay stage input terminal at the time of conduction of said first switching transistor; e. a second MOS transistor amplifier of substantially unity gain having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; f. a second MOS switching transistor having gate, source and drain electrodes, the source-drain path of said second MOS switching transistor being disposed serially between the output electrode of said first MOS transistor amplifier and the input electrode of said second MOS transistor amplifier, said second switching transistor providing, when rendered conducting, a low impedance conductive path between said output electrode of said first transistor amplifier and the input electrode of said second transistor amplifier for altering the charge on said last-named storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said output electrode of said first transistor amplifier at the time of conduction of said second switching transistor; g. means coupling said output electrode of said second MOS transistor amplifier to said delay stage output terminal; and h. means coupled to the gate electrodes of said first and second MOS switching transistors for alternately rendering said first and second switching transistors conducting so that a signal level appears at said delay stage output terminal at a time of conduction of said second switching transistor substantially corresponding in level to the signal level appearing at said delay stage input terminal during the immediately preceding time of conduction of said first switching transistor, and such signal level appearAnce at said delay stage output terminal persists during the immediately succeeding time of conduction of said first switching transistor.

Claim 3

Apparatus in accordance with claim 1 wherein said first and second switching transistors are of opposite channel conductivity type, and said means for alternately rendering said switching transistors conducting includes means for applying coinciding phases of a switching waveform to the respective gate electrodes of said first and second switching transistors.

Claim 4

Apparatus in accordance with claim 1 wherein said first and second switching transistors are of the same channel conductivity type, and said means for alternately rendering said switching transistors conducting includes means for applying mutually opposing phases of a switching waveform to the respective gate electrodes of said first and second switching transistors.

Claim 5

Apparatus in accordance with claim 3 also including third and fourth switching transistors, each having gate, source and drain electrodes but differing in channel conductivity type from said first and second switching transistors, wherein said third switching transistor has its source-drain path shunted across the source-drain path of said first switching transistor and its gate electrode connected to the gate electrode of said second switching transistor, and wherein said fourth switching transistor has its source-drain path shunted across the source-drain path of said second switching transistor and its gate electrode connected to the gate electrode of said first switching transistor.

Claim 6

Delay apparatus of the ''''bucket brigade'''' type comprising, in combination; a plurality of delay stages in cascade, each of said delay stages including: a. a delay stage input terminal; b. a delay stage output terminal; c. a first MOS transistor amplifier having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; d. a first MOS switching transistor having gate, source and drain electrodes, the source-drain path of said first MOS switching transistor being disposed serially between said delay stage input terminal and said input electrode of said first MOS transistor amplifier; e. a second MOS transistor amplifier having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; f. a second MOS switching transistor having gate, source and drain electrodes, the source-drain path of said second MOS switching transistor being disposed serially between the output electrode of said first MOS transistor amplifier and the input electrode of said second MOS transistor amplifier; g. means coupling said output electrode of said second MOS transistor amplifier to said delay stage output terminal; h. means coupled to the gate electrodes of said first and second MOS switching transistors for alternately rendering said first and second switching transistors conducting; and i. a first capacitor coupled between the gate electrode of said second switching transistor and the input electrode of said first transistor amplifier, and a second capacitor coupled between the gate electrode of said first switching transistor and the input electrode of said second transistor amplifier; and wherein said first and second switching transistors are of the same channel conductivity type, and said means for alternately rendering said switching transistors conducting includes means for applying mutually opposing phases of a switching waveform to the respective gate electrodes of said first and second switching transistors.

Claim 7

Delay apparatus of the ''''bucket brigade'''' type comprising, in combination; a plurality of delay stages in cascade, each of said delay stages including: a. a delay stage input terminal; b. a delay stage output terminal; c. a first MOS transistor amplifier having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; d. a first MOS switching transistor having gate, source and drain electrodes, the source-drain path of said first MOS switching transistor being disposed serially between said delay stage input terminal and said input electrode of said first MOS transistor amplifier; e. a second MOS transistor amplifier having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; f. a second MOS switching transistor having gate, source and drain electrodes, the source-drain path of said second MOS switching transistor being disposed serially between the output electrode of said first MOS transistor amplifier and the input electrode of said second MOS transistor amplifier; g. means coupling said output electrode of said second MOS transistor amplifier to said delay stage output terminal; h. means coupled to the gate electrodes of said first and second MOS switching transistors for alternately rendering said first and second switching transistors conducting; and i. a first capacitor coupled between the gate electrode of said second switching transistor and the input electrode of said first transistor amplifier, and a second capacitor coupled between the gate electrode of said first switching transistor and the input electrode of said second transistor amplifier; and wherein said first and second switching transistors are of the same channel conductivity type, and said means for alternately rendering said switching transistors conducting includes means for applying mutually opposing phases of a switching waveform to the respective gate electrodes of said first and second switching transistors.

Claim 8

Apparatus in accordance with claim 5 wherein said first and second capacitors substantially correspond in capacitance value to the respective gate-to-drain capacitances exhibited by said first and second switching transistors.

Claim 9

An integrated circuit analog signal delay line comprising, in combination on a common substrate,: a plurality of delAy stages in cascade, each of said delay stages including: a. a delay stage input terminal; b. a delay stage output terminal; c. a first MOS transistor amplifier having substantially unity gain and having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; d. a first MOS switching transistor having gate, source and drain electrodes, the source-drain path of said first MOS switching transistor being disposed serially between said delay stage input terminal and said input electrode of said first MOS transistor amplifier, said first switching transistor providing, when rendered conducting, a low impedance conductive path between said delay stage input terminal and said input electrode of said first transistor amplifier for altering the charge on said storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said delay stage input terminal at the time of conduction of said first switching transistor; e. a second MOS transistor amplifier having substantially unity gain and having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; f. a second MOS switching transistor having gate, source and drain electrodes, the source-drain path of said second MOS switching transistor being disposed serially between the output electrode of said first MOS transistor amplifier and the input electrode of said second MOS transistor amplifier, said second switching transistor providing, when rendered conducting, a low impedance conductive path between said output electrode of said first transistor amplifier and the input electrode of said second transistor amplifier for altering the charge on said last-named storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said output electrode of said first transistor amplifier at the time of conduction of said second switching transistor; g. means coupling said output electrode of said second MOS transistor amplifier to said delay stage output terminal; and h. a common switching waveform path connected to both of said gate electrodes, said first and second switching transistors being of opposite channel conductivity type.

Claim 10

An integrated circuit analog signal delay line comprising, in combination on a common substrate,: a plurality of delAy stages in cascade, each of said delay stages including: a. a delay stage input terminal; b. a delay stage output terminal; c. a first MOS transistor amplifier having substantially unity gain and having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; d. a first MOS switching transistor having gate, source and drain electrodes, the source-drain path of said first MOS switching transistor being disposed serially between said delay stage input terminal and said input electrode of said first MOS transistor amplifier, said first switching transistor providing, when rendered conducting, a low impedance conductive path between said delay stage input terminal and said input electrode of said first transistor amplifier for altering the charge on said storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said delay stage input terminal at the time of conduction of said first switching transistor; e. a second MOS transistor amplifier having substantially unity gain and having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; f. a second MOS switching transistor having gate, source and drain electrodes, the source-drain path of said second MOS switching transistor being disposed serially between the output electrode of said first MOS transistor amplifier and the input electrode of said second MOS transistor amplifier, said second switching transistor providing, when rendered conducting, a low impedance conductive path between said output electrode of said first transistor amplifier and the input electrode of said second transistor amplifier for altering the charge on said last-named storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said output electrode of said first transistor amplifier at the time of conduction of said second switching transistor; g. means coupling said output electrode of said second MOS transistor amplifier to said delay stage output terminal; and h. a common switching waveform path connected to both of said gate electrodes, said first and second switching transistors being of opposite channel conductivity type.

Claim 11

Apparatus in accordance with claim 7 wherein each of said transistor amplifiers includes, as a load impedance disposed on said common substrate, an MOS transistor having a source electrode connected to the respective amplifier output electrode, and gate and drain electrodes directly connected to each other.

Claim 12

An integrated circuit analog signal delay line comprising, in combination on a common substrate,: a plurality of delay stages in cascade, each of said delay stages including: a. a delay stage input terminal; b. a delay stage output terminal; c. a first MOS transistor amplifier having substantially unity gain and having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; d. a first MOS switching transistor having gate, source and drain electrodes, the source-drain path of said first MOS switching transistor being disposed serially between said delay stage input terminal and said input electrode of said first MOS transistor amplifier, said first switching transistor providing, when rendered conducting, a low impedance conductive path between said delay stage input terminal and said input electrode of said first transistor amplifier for altering the charge on said storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said delay stage input terminal at the time of conduction of said first switching transistor; e. a second MOS transistor amplifier having substantially unity gain and having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; f. a second MOS switching transiStor having gate, source and drain electrodes, the source-drain path of said second MOS switching transistor being disposed serially between the output electrode of said first MOS transistor amplifier and the input electrode of said second MOS transistor amplifier, said second switching transistor providing, when rendered conducting, a low impedance conductive path between said output electrode of said first transistor amplifier and the input electrode of said second transistor amplifier for altering the charge on said last-named storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said output electrode of said first transistor amplifier at the time of conduction of said second switching transistor; g. means coupling said output electrode of said second MOS transistor amplifier to said delay stage output terminal; and h. means, including mutually exclusive switching waveform paths connected to each of said gate electrodes, for alternately rendering conducting said first and second switching transistors so that a signal level appears at said delay stage output terminal at a time of conduction of said second switching transistor substantially corresponding in level to the signal level appearing at said delay stage input terminal during the immediately preceding time of conduction of said first switching transistor, and such signal level appearance at said delay stage output terminal persists during the immediately succeeding time of conduction of said first switching transistor.

Claim 13

An integrated circuit analog signal delay line comprising, in combination on a common substrate,: a plurality of delay stages in cascade, each of said delay stages including: a. a delay stage input terminal; b. a delay stage output terminal; c. a first MOS transistor amplifier having substantially unity gain and having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; d. a first MOS switching transistor having gate, source and drain electrodes, the source-drain path of said first MOS switching transistor being disposed serially between said delay stage input terminal and said input electrode of said first MOS transistor amplifier, said first switching transistor providing, when rendered conducting, a low impedance conductive path between said delay stage input terminal and said input electrode of said first transistor amplifier for altering the charge on said storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said delay stage input terminal at the time of conduction of said first switching transistor; e. a second MOS transistor amplifier having substantially unity gain and having an input electrode at which storage capacitance is exhibited, a common electrode and an output electrode; f. a second MOS switching transiStor having gate, source and drain electrodes, the source-drain path of said second MOS switching transistor being disposed serially between the output electrode of said first MOS transistor amplifier and the input electrode of said second MOS transistor amplifier, said second switching transistor providing, when rendered conducting, a low impedance conductive path between said output electrode of said first transistor amplifier and the input electrode of said second transistor amplifier for altering the charge on said last-named storage capacitance to establish a voltage level thereat substantially corresponding to the signal level at said output electrode of said first transistor amplifier at the time of conduction of said second switching transistor; g. means coupling said output electrode of said second MOS transistor amplifier to said delay stage output terminal; and h. means, including mutually exclusive switching waveform paths connected to each of said gate electrodes, for alternately rendering conducting said first and second switching transistors so that a signal level appears at said delay stage output terminal at a time of conduction of said second switching transistor substantially corresponding in level to the signal level appearing at said delay stage input terminal during the immediately preceding time of conduction of said first switching transistor, and such signal level appearance at said delay stage output terminal persists during the immediately succeeding time of conduction of said first switching transistor.

Claim 14

Apparatus in accordance with claim 9 wherein each of said transistor amplifiers includes (1) an MOS amplifier transistor having a gate electrode serving as said amplifier input electrode, a source electrode serving as said amplifier common electrode and a drain electrode serving as said amplifier output electrode, in association with (2) an MOS load transistor, substantially equal in geometrical size to said MOS amplifier transistor, having a source electrode connected to the associated amplifier transistor drain electrode, and conductively joined gate and drain electrodes, and wherein said MOS amplifier transistors and said MOS load transistors are of the same channel conductivity type as said MOS switching transistors.