Amplitude insensitive delay line

Claim 2

A circuit for delaying a signal comprising a plurality of cascaded saturating circuit elements wherein each element in the plurality of cascaded saturating circuit elements comprises: control means for varying delay through the element, the control means having a first node coupled to a voltage source, a second node and a third node wherein a signal may be placed on the third node in order to vary delay through the element; a first depletion-type MOSFET including a drain node coupled to the second node of the control means, a gate node coupled to a prior element and a source node coupled to a subsequent element; a first enhancement-type MOSFET including a drain node coupled to the source node of the first depletion-type MOSFET, a source node coupled to ground, and a gate node coupled to the prior element and to a gate note of a depletion-type MOSFET in the subsequent element.

Claim 3

A circuit as in claim 1 wherein: the control means comprises a second depletion-type MOSFET; the first node is a drain node; the second node is a source node; and, the third node is a gate node.

Claim 4

A circuit as in claim 2 wherein the gate node of the second depletion-type MOSFET is coupled to a node of a control means in the preceeding element and is coupled to a node of a control means in the subsequent element.

Claim 5

A circuit as in claim 1 wherein the control means comprises: a second depletion-type MOSFET having a drain node which is the first node, a source node, and a gate node which is the third node; and, a third depletion-type MOSFET having a drain node coupled to the source node of the second depletion-type MOSFET, a source node which is the second node, and a gate node coupled to the gate node of the second depletion-type MOSFET.

Claim 6

A circuit as in claim 4 wherein the third node is coupled to a node of a control means in the preceeding element and is coupled to a node of a control means in the subsequent element.

Claim 7

A circuit as in claim 1 wherein the control means comprises: a second depletion-type MOSFET having a drain node which is the first node, a source node which is the second node and a gate node which is the third node; and, a second enhancement-type MOSFET having a drain node coupled to the drain node of the second depletion-type MOSFET, a source node coupled to the source node of the second depletion-type MOSFET, and a gate node coupled to the gate node of the second depletion-type MOSFET.

Claim 8

A circuit as in claim 6 wherein the third node is coupled to a node of a control means in the preceeding element and is coupled to a node of a control means in the subsequent element.

Claim 9

A circuit for delaying a signal comprising: a plurality of cascaded saturating circuit elements; an input means for coupling the signal to the plurality of cascaded saturating circuit elements; an output means for coupling the signal to a subsequent circuit; and control means coupled to the plurality of cascaded saturating circuit elements for varying the length of time the signal is delayed, the control means comprising a plurality of taps at intervals of delay along the plurality of cascaded saturating circuit elements, and a switching means coupled to the plurality of taps and to the output means for allowing external selection of a tap from the plurality of taps to be coupled to the output means, the switching means comprising layers of switches wherein: a first layer of switches comprises a first plurality of logic switches each switch having a first input pole coupled to a first tap of the plurality of taps, a second input pole coupled to a second tap of the plurality of taps, and an output node; a second layer of switches comprises a second plurality of logic switches each switch having a first input pole coupled to a first output node of a switch from the first plurality of logic switches, a second input pole coupled to a second output node of a switch from the first plurality of logic switches, and an output node; and, a last layer of switches comprising a logic switch having a first pole coupled to a first output node of a switch from a prior layer of switches, a second pole coupled to a second output node of switch from the prior layer of switches, and an output node coupled to the output means.

Claim 10

A circuit for delaying a signal comprising: a plurality of cascaded saturating circuit elements; an input means for coupling the signal to the plurality of cascaded saturating circuit elements; an output means for coupling the signal to a subsequent circuit; and control means coupled to the plurality of cascaded saturating circuit elements for varying the length of time the signal is delayed, the control means comprising a plurality of taps at intervals of delay along the plurality of cascaded saturating circuit elements, and a switching means coupled to the plurality of taps and to the output means for allowing external selection of a tap from the plurality of taps to be coupled to the output means, the switching means comprising layers of switches wherein: a first layer of switches comprises a first plurality of logic switches each switch having a first input pole coupled to a first tap of the plurality of taps, a second input pole coupled to a second tap of the plurality of taps, and an output node; a second layer of switches comprises a second plurality of logic switches each switch having a first input pole coupled to a first output node of a switch from the first plurality of logic switches, a second input pole coupled to a second output node of a switch from the first plurality of logic switches, and an output node; and, a last layer of switches comprising a logic switch having a first pole coupled to a first output node of a switch from a prior layer of switches, a second pole coupled to a second output node of switch from the prior layer of switches, and an output node coupled to the output means.

Claim 11

A circuit as in claim 8 wherein the plurality of taps are at equal intervals of delay.

Claim 12

A circuit for delaying a signal comprising a plurality of cascaded saturating circuit elements wherein each element in the plurality of cascaded saturating circuit elements comprises: an inverter; control means for varying the length of delay through the inverter, the control means comprising a first depletion-type MOSFET having a first node coupled to a voltage source, a second node and a third node on which may be placed a signal in order to vary delay through the inverter a second depletion-type MOSFET having a first node coupled to the inverter, a second node which is coupled to the second node of the first depletion-type MOSFET, and a third node coupled to the third node of the first depletion-type MOSFET.

Claim 13

A circuit for delaying a signal comprising a plurality of cascaded saturating circuit elements wherein each element in the plurality of cascaded saturating circuit elements comprises: an inverter; control means for varying the length of delay through the inverter, the control means comprising a first depletion-type MOSFET having a first node coupled to a voltage source, a second node and a third node on which may be placed a signal in order to vary delay through the inverter a second depletion-type MOSFET having a first node coupled to the inverter, a second node which is coupled to the second node of the first depletion-type MOSFET, and a third node coupled to the third node of the first depletion-type MOSFET.

Claim 14

A circuit as in claim 10 wherein the third node of the first depletion-type MOSFET is coupled to a node of a control means in the preceeding element and is coupled to a node of a control means in the subsequent element.

Claim 15

A circuit for delaying a signal comprising a plurality of cascaded saturating circuit elements wherein each element in the plurality of cascaded saturating circuit elements comprises: an inverter; control means for varying the length of dely through the inverter, the control means comprising a depletion-type MOSFET having a first node coupled to a voltage source, a second node coupled to the inverter and a third node on which may be placed a signal in order to vary delay through the inverter, and an enhancement-type MOSFET having a first node coupled to the first node of the depletion-type MOSFET, a second node coupled to the second node of the depletion-type MOSFET, and a third node coupled to the third node of the depletion-type MOSFET.

Claim 16

A circuit for delaying a signal comprising a plurality of cascaded saturating circuit elements wherein each element in the plurality of cascaded saturating circuit elements comprises: an inverter; control means for varying the length of dely through the inverter, the control means comprising a depletion-type MOSFET having a first node coupled to a voltage source, a second node coupled to the inverter and a third node on which may be placed a signal in order to vary delay through the inverter, and an enhancement-type MOSFET having a first node coupled to the first node of the depletion-type MOSFET, a second node coupled to the second node of the depletion-type MOSFET, and a third node coupled to the third node of the depletion-type MOSFET.

Claim 17

A circuit as in claim 12 wherein the third node of the depletion-type MOSFET is coupled to a node of a control means in the preceeding element and is coupled to a node of a control means in the subsequent element.