US4491747A
Expired / Lapsed
US
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Logic circuit using depletion mode field effect switching transistors
Assignee: Toshiba Corp
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Filing: 1982-09-29
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Granted: 1985-01-01
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Expires: 2002-09-29
Abstract
Abstract A logic circuit using depletion-mode field effect switching transistors, wherein, a plurality of logic elements respectively having at least one depletion-mode switching FET are connected in series. The source electrodes of the switching FETs are maintained at a voltage higher by a predetermined voltage than ground potential by the Schottky diode and connected commonly to each other. The switching FETs are connected at the drain electrodes through active loads to a power source terminal supplied with one type of external DC power source voltage. The drain potential of the switching FETs is level-shifted to a predetermined voltage higher than the gate potential of the FETs in the next stage. The FETs are provided between the diodes and ground to prevent the variation in the level shift voltage.
Inventors
- 👤 Shoichi Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:02
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
301 words
A circuit for performing a logic operation on an input signal supplied to an input terminal and supplying an output signal from an output terminal, said circuit comprising: (a) first and second terminals between which an external power source is connected and which are supplied with first and second voltages, respectively, the first voltage being higher than the second voltage; (b) a plurality of logic elements connected in cascade between the signal input and output terminals, each of said logic elements including at least one switching transistor which comprises a depletion-mode field effect transistor having gate, drain and source electrodes, the source electrodes of the switching field effect transistors being connected to each other; (c) load means connected between said first terminal and the drain electrode of each of said switching field effect transistors, for receiving an electric power from the external power source and for supplying a substantially constant current to said switching field effect transistor; (d) voltage level-controlling means, connected between the second terminal and the connection point of the source electrodes of said switching field effect transistors, for maintaining the source electrodes at a predetermined third voltage lower than the first voltage and higher than the second voltage; and (e) level-shifting means for level-shifting the voltage at the drain electrodes of one switching field effect transistor of each logic element by a predetermined potential difference and applying the level-shifted drain electrode voltage to the gate electrode of said switching field effect transistor in the next succeeding logic element, said predetermined potential difference being such that a logic high voltage at said drain electrode of said switching field effect transistor biases said succeeding switching transistor into conductance, and a logic low voltage at said drain electrode of said switching field effect transistor biases said succeeding switching transistor into nonconductance.
Claim 2
Dependent Claim
301 words
A circuit for performing a logic operation on an input signal supplied to an input terminal and supplying an output signal from an output terminal, said circuit comprising: (a) first and second terminals between which an external power source is connected and which are supplied with first and second voltages, respectively, the first voltage being higher than the second voltage; (b) a plurality of logic elements connected in cascade between the signal input and output terminals, each of said logic elements including at least one switching transistor which comprises a depletion-mode field effect transistor having gate, drain and source electrodes, the source electrodes of the switching field effect transistors being connected to each other; (c) load means connected between said first terminal and the drain electrode of each of said switching field effect transistors, for receiving an electric power from the external power source and for supplying a substantially constant current to said switching field effect transistor; (d) voltage level-controlling means, connected between the second terminal and the connection point of the source electrodes of said switching field effect transistors, for maintaining the source electrodes at a predetermined third voltage lower than the first voltage and higher than the second voltage; and (e) level-shifting means for level-shifting the voltage at the drain electrodes of one switching field effect transistor of each logic element by a predetermined potential difference and applying the level-shifted drain electrode voltage to the gate electrode of said switching field effect transistor in the next succeeding logic element, said predetermined potential difference being such that a logic high voltage at said drain electrode of said switching field effect transistor biases said succeeding switching transistor into conductance, and a logic low voltage at said drain electrode of said switching field effect transistor biases said succeeding switching transistor into nonconductance.
Claim 3
Dependent Claim
38 words
A circuit according to claim 1, wherein said load means comprises a plurality of depletion-mode field effect transistors each having its respective gate electrode connected to its source electrode and a drain electrode connected to said first terminal.
Claim 4
Dependent Claim
59 words
A circuit according to claim 1, wherein said voltage level-controlling means comprises at least one voltage level-controlling device which receives substantially constant current flowing from the source electrodes of said switching field effect transistors to said second terminal and which generates a voltage drop therein in response to the current, thereby maintaining the source electrodes at the third voltage.
Claim 5
Dependent Claim
78 words
A circuit according to claim 1, wherein said voltage level-controlling means comprises a plurality of voltage level-controlling devices which receive substantially constant current flowing from the source electrodes of said switching field effect transistors to said second terminal and which generate a voltage drop therein in response to the current, thereby maintaining the source electrodes at the third voltage, said voltage level controlling devices being connected between said source electrodes and second terminal in parallel with each other.
Claim 6
Dependent Claim
14 words
A circuit according to claim 3, wherein said voltage level-controlling device comprises a resistor.
Claim 7
Dependent Claim
37 words
A circuit according to claim 3, wherein said voltage level-controlling device comprises a semiconductor diode having an anode connected to the source electrodes of said switching field effect transistors and a cathode connected to said second terminal.
Claim 8
Dependent Claim
14 words
A circuit according to claim 6, wherein said semiconductor diode comprises a Schottky diode.
Claim 9
Dependent Claim
18 words
A circuit according to claim 3, wherein said voltage level-controlling device comprises a plurality of series-connected semiconductor diodes.
Claim 10
Dependent Claim
41 words
A circuit according to claim 1, which further comprises means connected in parallel with said voltage level-controlling means and to said second terminal, for suppressing the variation in the third voltage and for preventing the variation in the level shift voltage.
Claim 11
Dependent Claim
59 words
A circuit according to claim 9, which further comprises means for absorbing pulse noise generated at the commonly connected source electrodes of said switching field effect transistors, said pulse noise absorbing means including at least one reverse-biased semiconductor diode having an anode electrode connected to said second terminal and a cathode electrode connected to said commonly connected source electrodes.
Claim 12
Dependent Claim
38 words
A circuit according to claim 9, wherein said level-shift voltage variation-suppressing means comprises a deletion-mode field effect transistor having a drain electrode connected to said level-shifting means and gate and source electrodes commonly connected to said second terminal.
Claim 13
Dependent Claim
36 words
A circuit according to claim 1, wherein said level-shifting means comprises a level shifting device connected between at least a pair of switching field effect transistors respectively included in said logic elements adjacent to each other.
Claim 14
Dependent Claim
50 words
A circuit according to claim 12, wherein said level-shifting device is connected between the drain electrode of the switching field effect transistor of the previous logic element of said pair of switching field effect transistors and the gate electrode of the switching field effect transistor of the following logic element.
Claim 15
Dependent Claim
33 words
A circuit according to claim 13, wherein said level-shifting device includes at least one semiconductor diode having a cathode electrode connected to the gate electrode of said following stage switching field effect transistor.
Claim 16
Dependent Claim
13 words
A circuit according to claim 13, wherein said level-shifting device includes a resistor.
Claim 17
Dependent Claim
20 words
A circuit according to claim 13, wherein said level-shifting device includes a series connection of a plurality of semiconductor diodes.
Claim 18
Dependent Claim
19 words
A circuit according to any one of claims 14 or 16, wherein said semiconductor diode includes a Schottky diode.
Claim 19
Dependent Claim
59 words
A circuit according to claim 13, wherein said level-shifting device includes a depletion-mode field effect transistor having a drain electrode connected to said first terminal, gate electrode connected to the drain electrode of said previous logic element switching field effect transistor and a source electrode connected to the gate electrode of said following logic element switching field effect transistor.
Claim 20
Dependent Claim
35 words
A circuit according to claim 1, wherein at least one of said logic elements includes a plurality of switching transistors having their drain-source current paths connected in parallel and which are depletion-mode field effect transistors.
Claim 21
Dependent Claim
35 words
A circuit according to claim 1, wherein at least one of said logic elements includes a plurality of switching transistors which are depletion-mode field effect transistors and which are connected in series with each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-01 | 1988-07-02 | 1989-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-01 | 1992-07-02 | 1993-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-01 | 1996-07-02 | 1997-01-01 | $7700.00 | Window Closed / Lapsed |