Logic circuits-employing junction-type field-effect transistors

Claim 2

A logic circuit integrated upon a semi-insulating substrate comprising a d.c. supply, a junction type field-effect transistor having ion implanted source drain and channel regions, having a predetermined type of conductivity and a metal gate forming with said channel a Schottky junction, said channel having a thickness equal to that of the depletion zone produced by a zero potential applied to said gate junction, said logic circuit comprising at least two inputs and one output, means for carrying selectively said inputs at two predetermined voltage values corresponding respectively to the digit 0 and the digit 1, first resistor means for connecting said drain to said d.c. supply, said output being connected to said drain, said source being grounded, second resistor means for connecting said gate to ground, for applying to said gate a voltage near zero; rectifying means for connecting selectively said inputs to said carrying means for establishing a first conduction path between at least one of said inputs and said supply where said at least one input is at the 0 level, means for establishing a second conductive path between said d.c. supply and the ground, where all the rectifying means are not conductive, and giving to said gate a voltage rendering said transistor conductive.

Claim 3

A logic circuit as claimed in claim 1, wherein said source, drain and channels are of the n type of conductivity, said substrate having a doping concentration of the order of 10 14 at/cm 3 , said source and drains a doping concentration of the order of 10 20 at/cm.sup. 3, said channel a doping concentration of about 10 16 at/cm 3 and a thickness near 0.4 micron.

Claim 4

An integrated logic circuit element comprising: a first and second d.c. supply of opposite polarities, said first supply supplying a voltage substantially equal to 2.5 volts and said second supply supplying a voltage between 0 and 0.5 volt in absolute value, a junction type field effect transistor including a gate electrode, source and drain regions and having an n type channel with a thickness equal to that of the depletion zone obtained by applying to said gate the source potential and comprising at least two inputs and one output, and means for carrying selectively said inputs at two predetermined level values significant respectively the digit 0 and the digit 1; first resistor means for connecting said drain to said first supply; said output being connected to said drain, and the source of said transistor being grounded, second resistor means connecting the gate of the transistor to the second supply, for applying to said gate a voltage comprised between 0 and approximately 1 volt; rectifying means for connecting respectively said inputs to said first supply, for establishing a first conduction path between at least one of said inputs and said first supply, when said at least one of said inputs is at the level 0, said gate being at a potential level, rendering said transistor blocked, means for establishing a second conduction path between said first and said second supply when all said rectifying means are not conductive, and giving to said gate a voltage rendering said transistor conductive, said establishing means including several diodes cascade connected and biased in the forward directions, when said rectifying means are all blocked.

Claim 5

An integrated logic circuit element comprising: a first and second d.c. supply of opposite polarities, said first supply supplying a voltage substantially equal to 2.5 volts and said second supply supplying a voltage between 0 and 0.5 volt in absolute value, a junction type field effect transistor including a gate electrode, source and drain regions and having an n type channel with a thickness equal to that of the depletion zone obtained by applying to said gate the source potential and comprising at least two inputs and one output, and means for carrying selectively said inputs at two predetermined level values significant respectively the digit 0 and the digit 1; first resistor means for connecting said drain to said first supply; said output being connected to said drain, and the source of said transistor being grounded, second resistor means connecting the gate of the transistor to the second supply, for applying to said gate a voltage comprised between 0 and approximately 1 volt; rectifying means for connecting respectively said inputs to said first supply, for establishing a first conduction path between at least one of said inputs and said first supply, when said at least one of said inputs is at the level 0, said gate being at a potential level, rendering said transistor blocked, means for establishing a second conduction path between said first and said second supply when all said rectifying means are not conductive, and giving to said gate a voltage rendering said transistor conductive, said establishing means including several diodes cascade connected and biased in the forward directions, when said rectifying means are all blocked.