Asynchronous digital delay line

Claim 2

An asynchronous digital delay line for delaying amplitude limited frequency modulated impulses of predetermined constant short duration carrying information on the leading edges thereof comprising a plurality of digital gates connected in cascade to form a tandem array wherein each gate provides a known increment of delay and wherein at least one of said gates additionally comprises pulse restoration means for regenerating said impulses passing through said delay line to be of said predetermined constant short duration.

Claim 3

An asynchronous digital delay line for delaying amplitude limited frequency modulated pulses carrying all information on the leading edges thereof comprising a plurality of digital gates connected in cascade to form a tandem array through which said impulses pass by self-clocking and wherein each gate provides a known increment of delay and further including at least one said gate thereof comprising pulse restoration means having a connection to an output of a following gate for regenerating each said impulse passing therethrough to be of said predetermined short duration.

Claim 4

An asynchronous digital delay line for delaying amplitude limited frequency modulated pulses carrying all information on the leading edges thereof comprising a plurality of digital gates connected in cascade to form a tandem array through which said impulses pass by self-clocking and wherein each gate provides a known increment of delay and further including at least one said gate thereof comprising pulse restoration means having a connection to an output of a following gate for regenerating each said impulse passing therethrough to be of said predetermined short duration.

Claim 5

A tapped digital delay line for delaying amplitude limited frequency modulated pulses wherein all information is contained on the leading edges of said pulses of a continuously connected plurality of delay elements with taps therebetween each element providing an increment of delay and comprising a plurality of digital gates connected in series including within said series a first two input NAND gate having a first input connected to receive said pulses and having a second input and an output; a second two input NAND gate having a first input connected to said output of said first gate and a second input and an output; an inverter gate having an input connected to said output of said second gate and an output connected to another of said gates in said series; a third two input NAND gate having a first input connected to said output of said second gate, a second input connected to said output of said inverter gate and to said second input of said first gate and an output connected to said second input of said second gate; and further comprising multiplexer means connected to said taps for selecting one of said taps in response to a tap selection control signal provided for controlling the delay length of said tapped digital delay lines.

Claim 6

A tapped digital delay line for delaying amplitude limited frequency modulated pulses wherein all information is contained on the leading edges of said pulses of a continuously connected plurality of delay elements with taps therebetween each element providing an increment of delay and comprising a plurality of digital gates connected in series including within said series a first two input NAND gate having a first input connected to receive said pulses and having a second input and an output; a second two input NAND gate having a first input connected to said output of said first gate and a second input and an output; an inverter gate having an input connected to said output of said second gate and an output connected to another of said gates in said series; a third two input NAND gate having a first input connected to said output of said second gate, a second input connected to said output of said inverter gate and to said second input of said first gate and an output connected to said second input of said second gate; and further comprising multiplexer means connected to said taps for selecting one of said taps in response to a tap selection control signal provided for controlling the delay length of said tapped digital delay lines.

Claim 7

An asynchronous digital delay line for delaying amplitude limited frequency modulated pulses carrying all information on the leading edges thereof comprising a plurality of digital gates connected in cascade to form a tandem array through which said impulses pass by self clocking and wherein each gate provides a known increment of delay and wherein at least one said gate thereof comprises a part of a latch connected flip flop, the input to said gate being a set input of said flip flop and a reset input thereof being provided by a reset connection from an output of another said gate of said array following said one said gate, said flip flop for regenerating said impulses passing through said delay line to be of said predetermined constant short duration.

Claim 8

An asynchronous digital delay line for delaying amplitude limited frequency modulated pulses carrying all information on the leading edges thereof comprising a plurality of digital gates connected in cascade to form a tandem array through which said impulses pass by self clocking and wherein each gate provides a known increment of delay and wherein at least one said gate thereof comprises a part of a latch connected flip flop, the input to said gate being a set input of said flip flop and a reset input thereof being provided by a reset connection from an output of another said gate of said array following said one said gate, said flip flop for regenerating said impulses passing through said delay line to be of said predetermined constant short duration.

Claim 9

The asynchronous digital delay line set forth in claim 4 wherein said reset connection is also connected to an input of a gate of said array immediately preceding said one gate comprising a part of said flip flop.