US3641371A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay system for regenerating pulse periodically during delay interval
Assignee: Individual
•
Filing: 1970-06-12
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Granted: 1972-02-08
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Expires: 1990-06-12
Abstract
Abstract A time delay system capable of delaying very fast pulses for a relatively long time without appreciable distortion by regenerating the pulse periodically during the delay interval. Each regenerated pulse is used to regenerate the next pulse. In preferred form, regeneration is accomplished in amplifiers or ''''switches'''' which are polarity sensitive. The pulse to be delayed is applied to a delay circuit which reflects it back to the input terminal with inverted polarity. The regenerating ''''switch'''' is responsive to the reflection to initiate a new pulse. Two delay circuits are shown. One employs a delay line and utilizes the inherent broad band characteristics of such lines to reproduce rectangular pulses after a delay. The other employs a tuned circuit in a narrow band delay system.
Inventors
- 👤 Victor F Cartwright
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:12
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/02; G01S13/06; G01S13/08; G01S13/10; G01S13/18; H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; H03K; H03K3/00; H03K3/80; H03K5/00; H03K5/01; H03K5/04; H03K5/06; H03K5/065
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
95 words
In a delay system: a first and a second delay means including a parallel L-C circuit each for providing an output pulse of given polarity in response to a previously applied pulse of opposite polarity; and application means for applying an input signal to the second delay means as an incident to provision of an output signal by the first delay means; said first and second delay means each comprising an emitterfollower and a phase reversing amplifier in that order and which further comprises an emitter-follower in parallel with the emitter-follower of each delay means.
Claim 2
Dependent Claim
95 words
In a delay system: a first and a second delay means including a parallel L-C circuit each for providing an output pulse of given polarity in response to a previously applied pulse of opposite polarity; and application means for applying an input signal to the second delay means as an incident to provision of an output signal by the first delay means; said first and second delay means each comprising an emitterfollower and a phase reversing amplifier in that order and which further comprises an emitter-follower in parallel with the emitter-follower of each delay means.
Claim 3
Dependent Claim
93 words
In a pulse delay system, in combination: first and second delay circuit means for receiving input pulses of one polarity and, after a time delay, issuing output pulses of opposite polarity, first and second switch means connected in parallel with said first and second delay circuit means, respectively, for providing a delayed pulse in response to said output pulses, and means for receiving the output pulse issued from said first delay circuit means and inverting it and applying the inverted pulse to the second delay circuit means and to the second switch means.
Claim 4
Dependent Claim
93 words
In a pulse delay system, in combination: first and second delay circuit means for receiving input pulses of one polarity and, after a time delay, issuing output pulses of opposite polarity, first and second switch means connected in parallel with said first and second delay circuit means, respectively, for providing a delayed pulse in response to said output pulses, and means for receiving the output pulse issued from said first delay circuit means and inverting it and applying the inverted pulse to the second delay circuit means and to the second switch means.
Claim 5
Dependent Claim
16 words
The invention defined in claim 2 in which said first and second switches comprise cathode followers.
Claim 6
Dependent Claim
53 words
The invention defined in claim 2 which further comprises a pair of gates and third and fourth switch means each connected between an associated one of said delay means and an associated one of said gates for furnishing a signal to the gate in response to the output pulse of the delay means.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-02-07 | 1975-08-09 | 1976-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-02-07 | 1979-08-09 | 1980-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-02-07 | 1983-08-09 | 1984-02-08 | $7700.00 | Window Closed / Lapsed |