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US3226567A Expired / Lapsed US ⏱️ 0.0 years remaining

Active time delay devices

Assignee: Lockheed Martin Corp
•
Filing: 1962-02-05
•
Granted: 1965-12-28
•
Expires: 1982-02-05
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Abstract

No abstract record available.

Inventors

  • 👤 Richard W Bradmiller
  • 👤 James A Almond

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 21:25
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/145

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 271 words
AN ACTICE DELAY DEVICE HAVING A HIGH INPUT IMPEDANCE AND A LOW OUTPUT IMPEDANCE FOR PROVIDING AN OUTPUT SIGNAL WHICH IS DELAYED A PREDETERMINED PERIOD WITH RESPECT TO THE INPUT SIGNAL AND HAS A PREDETERMINED WIDTH INDEPENDENT OF THE WIDTH OF SAID INPUT SIGNAL, SAID DEVICE COMPRISING: (A) A TRANSISTOR HAVING BASE, EMITTER AND COLLECTOR CIRCUITS AND AN OUTPUT LOAD RESISTOR CONNECTED ACROSS SAID COLLECTOR CIRCUIT; (B) A REACTIVE LOAD CONNECTED TO SAID COLLECTOR CIRCUIT IN PARALLEL TO SAID OUTPUT LOAD RESISTOR; (C) MEANS FOR APPLYING AN INPUT SIGNAL TO THE BASE OF SAID TRANSISTOR; (D) MEANS FOR BIASING SAID TRANSISTOR TO CLASS A OPERATION SO THAT ENERGY IS PROVIDED TO SAID REACTIVE LOAD WHEN SAID INPUT SIGNAL IS COUPLED TO SAID BASE CIRCUIT SO AS TO SHOCK ACROSS SAID REACTIVE LOAD; PRODUCE A VOLTAGE SIGNAL ACROSS SAID REACTIVE LOAD; (E) SAID VOLTAGE SIGNAL HAVING EXCURSIONS OF ONE POLARITY AND VOLTAGE EXCURSIONS OF ANOTHER POLARITY; (F) A FIRST DIODE CONNECTED ACROSS SAID REACTIVE LOAD AND BEING POLED SO A STO PASS SAID VOLTAGE EXCURSIONS OF ONE POLARITY AND BLOCK SAID VOLTAGE EXCURSIONS OF ANOTHER POLARITY; (G) A SECOND DIODE SERIES CONNECTED BETWEEN SAID REACTIVE LOAD AND SAID OUTPUT LOAD RESISTOR AND BEING POLED SO AS TO BLOCK SAID VOLTAGE EXCURSIONS OF ANOTHER POLARITY AND PASS SAID VOLTAGE EXCURSIONS OF ON POLARITY; AND (H) SAID FIRST DIODE BEING FURTHER ADAPTED TO PASS SAID VOLTAGE EXCURSIONS OF ONE POLARITY WHEN SAID INPUT SIGNAL IS COUPLED TO SAID BASE CIRCUIT AND, WHEREBY SAID FIRST DIODE WILL SHORT SAID VOLTAGE EXCURSIONS OF ONE POLARITY ONLY WHEN SAID INPUT SIGNAL IS DECOUPLED FROM SAID BASE CIRCUIT.
Claim 2
Dependent Claim 271 words
AN ACTICE DELAY DEVICE HAVING A HIGH INPUT IMPEDANCE AND A LOW OUTPUT IMPEDANCE FOR PROVIDING AN OUTPUT SIGNAL WHICH IS DELAYED A PREDETERMINED PERIOD WITH RESPECT TO THE INPUT SIGNAL AND HAS A PREDETERMINED WIDTH INDEPENDENT OF THE WIDTH OF SAID INPUT SIGNAL, SAID DEVICE COMPRISING: (A) A TRANSISTOR HAVING BASE, EMITTER AND COLLECTOR CIRCUITS AND AN OUTPUT LOAD RESISTOR CONNECTED ACROSS SAID COLLECTOR CIRCUIT; (B) A REACTIVE LOAD CONNECTED TO SAID COLLECTOR CIRCUIT IN PARALLEL TO SAID OUTPUT LOAD RESISTOR; (C) MEANS FOR APPLYING AN INPUT SIGNAL TO THE BASE OF SAID TRANSISTOR; (D) MEANS FOR BIASING SAID TRANSISTOR TO CLASS A OPERATION SO THAT ENERGY IS PROVIDED TO SAID REACTIVE LOAD WHEN SAID INPUT SIGNAL IS COUPLED TO SAID BASE CIRCUIT SO AS TO SHOCK ACROSS SAID REACTIVE LOAD; PRODUCE A VOLTAGE SIGNAL ACROSS SAID REACTIVE LOAD; (E) SAID VOLTAGE SIGNAL HAVING EXCURSIONS OF ONE POLARITY AND VOLTAGE EXCURSIONS OF ANOTHER POLARITY; (F) A FIRST DIODE CONNECTED ACROSS SAID REACTIVE LOAD AND BEING POLED SO A STO PASS SAID VOLTAGE EXCURSIONS OF ONE POLARITY AND BLOCK SAID VOLTAGE EXCURSIONS OF ANOTHER POLARITY; (G) A SECOND DIODE SERIES CONNECTED BETWEEN SAID REACTIVE LOAD AND SAID OUTPUT LOAD RESISTOR AND BEING POLED SO AS TO BLOCK SAID VOLTAGE EXCURSIONS OF ANOTHER POLARITY AND PASS SAID VOLTAGE EXCURSIONS OF ON POLARITY; AND (H) SAID FIRST DIODE BEING FURTHER ADAPTED TO PASS SAID VOLTAGE EXCURSIONS OF ONE POLARITY WHEN SAID INPUT SIGNAL IS COUPLED TO SAID BASE CIRCUIT AND, WHEREBY SAID FIRST DIODE WILL SHORT SAID VOLTAGE EXCURSIONS OF ONE POLARITY ONLY WHEN SAID INPUT SIGNAL IS DECOUPLED FROM SAID BASE CIRCUIT.

References Cited (Backward Citations)

US2443619A Cited
US2594336A Cited
US3011066A Cited
US2875336A Cited
US2914683A Cited
US2924724A Cited
US3047734A Cited
US2971164A Cited
US3076103A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1968-12-27 1969-06-28 1969-12-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1972-12-27 1973-06-28 1973-12-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1976-12-27 1977-06-28 1977-12-28 $7700.00 Window Closed / Lapsed

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