Scanning circuit to deliver train of pulses shifted by a constant delay one after another

Claim 2

A scanning circuit comprising: a circuit means consisting of a plurality of cascade-connected circuits, each unit circuit having a first and a second polarity inverting circuit and the output of said first polarity inverting circuit being fed as an input to said second polarity inverting circuit; a first power source means to supply DC power for each of said unit circuits; an input means to apply an input signal to the first stage of said circuit means; and an output means to take out the output of said second polarity inverting circuit of each of said unit circuits, wherein said first polarity inverting circuit includes a first and a second MOS transistor, each transistor having an input terminal and first and second output terminals, and said second polarity inverting circuit includes a third and a fourth MOS transistor, each transistor having an input terminal and first and second output terminals, said input terminal and said first output terminal of each of said first and third transistors being commonly connected with one terminal of said first power source means, said second output terminals of said first and third transistors being connected with said first output terminals of said second and fourth transistors, respectively, said second output terminals of said second and fourth transistors being connected with the other terminal of said first power source means, said first output terminal of said second transistor being connected with said input terminal of said fourth transistor, said first output terminal of said fourth transistor being connected with said output means; further comprising a second power source means and a fifth MOS transistor provided in each unit circuit of said circuit means, said fifth transistor having an input terminal and a first and a second output terminal, said input terminal of said fifth transistor being connected with said second power source means, and said first and second output terminals of said fifth transistor being connected respectively with said first output terminal of said second transistor and said input terminal of said fourth transistor.

Claim 3

A scanning circuit comprising: a circuit means consisting of a plurality of cascade-connected circuits, each unit circuit having a first and a second polarity inverting circuit and the output of said first polarity inverting circuit being fed as an input to said second polarity inverting circuit; a first power source means to supply DC power for each of said unit circuits; an input means to apply an input signal to the first stage of said circuit means; and an output means to take out the output of said second polarity inverting circuit of each of said unit circuits, wherein said first polarity inverting circuit includes a first and a second MOS transistor, each transistor having an input terminal and first and second output terminals, and said second polarity inverting circuit includes a third and a fourth MOS transistor, each transistor having an input terminal and first and second output terminals, said input terminal and said first output terminal of each of said first and third transistors being commonly connected with one terminal of said first power source means, said second output terminals of said first and third transistors being connected with said first output terminals of said second and fourth transistors, respectively, said second output terminals of said second and fourth transistors being connected with the other terminal of said first power source means, said first output terminal of said second transistor being connected with said input terminal of said fourth transistor, said first output terminal of said fourth transistor being connected with said output means, further comprising a second power source means and a fifth MOS transistor provided in each unit circuit of said circuit means, said fifth transistor having an input terminal and a first and a second output terminal, said input terminal of said fifth transistor being connected with said second power source means, and said first and second output terminals of said fifth transistor being connected respectively with said first output terminal of said second transistor and said input terminal of said fourth transistor; further comprising in each unit circuit of said circuit means a sixth MOS transistor having an input terminal and a first and a second output terminal, said input terminal of said sixth transistor being connected with said second power source means and said first and second output terminals of said sixth transistor being connected respectively with said first output terminal of said fourth transistor and said output means.

Claim 4

A scanning circuit comprising: a circuit means consisting of a plurality of cascade-connected circuits, each unit circuit having a first and a second polarity inverting circuit and the output of said first polarity inverting circuit being fed as an input to said second polarity inverting circuit; a first power source means to supply DC power for each of said unit circuits; an input means to apply an input signal to the first stage of said circuit means; and an output means to take out the output of said second polarity inverting circuit of each of said unit circuits, wherein said first polarity inverting circuit includes a first and a second MOS transistor, each transistor having an input terminal and first and second output terminals, and said second polarity inverting circuit includes a third and a fourth MOS transistor, each transistor having an input terminal and first and second output terminals, said input terminal and said first output terminal of each of said first and third transistors being commonly connected with one terminal of said first power source means, said second output terminals of said first and third transistors being connected with said first output terminals of said second and fourth transistors, respectively, said second output terminals of said second and fourth transistors being connected with the other terminal of said first power source means, said first output terminal of said second transistor being connected with said input terminal of said fourth transistor, said first output terminal of said fourth transistor being connected with said output means, further comprising a second power source means and a fifth MOS transistor provided in each unit circuit of said circuit means, said fifth transistor having an input terminal and a first and a second output terminal, said input terminal of said fifth transistor being connected with said second power source means, and said first and second output terminals of said fifth transistor being connected respectively with said first output terminal of said second transistor and said input terminal of said fourth transistor; further comprising in each unit circuit of said circuit means a sixth MOS transistor having an input terminal and a first and a second output terminal, said input terminal of said sixth transistor being connected with said second power source means and said first and second output terminals of said sixth transistor being connected respectively with said first output terminal of said fourth transistor and said output means.

Claim 5

A scanning circuit comprising: a circuit means consisting of a plurality of cascade-connected unit circuits, each unit circuit having a first and a second polarity inverting circuits and the output of said first polarity inverting circuit being fed as an input to said second polarity inverting circuit; a first and a second power source means to supply DC power for each of said unit circuits; an input means to apply an input signal to the first stage of said circuit means; and an output means to take out the output of said second polarity inverting circuit of each of said unit circuits; wherein said first polarity inverting circuit consists of a first and a second transistor and said second polarity inverting circuit consists of a third and a fourth transistors, each said first, second, third and fourth transistors having an input terminal and first and second output terminals and said first output terminal of each of said first and third transistors being commonly connected with one end of said first power source means, said second output terminals of said first and third transistors being connected respectively with said first output terminals of said second and fourth transistors, said second output terminals of said second and fourth transistors being connected with the other end of said first power source means; each unit circuit further including a fifth transistor having an input terminal connected with said second power source means, a first output terminal connected with one of said first output terminals of said second and fourth transistors and a second output terminal connected with one of said input terminals of said fourth transistor and said output means.

Claim 6

A scanning circuit comprising: a circuit means consisting of a plurality of cascade-connected unit circuits, each unit circuit having a first and a second polarity inverting circuits and the output of said first polarity inverting circuit being fed as an input to said second polarity inverting circuit; a first and a second power source means to supply DC power for each of said unit circuits; an input means to apply an input signal to the first stage of said circuit means; and an output means to take out the output of said second polarity inverting circuit of each of said unit circuits; wherein said first polarity inverting circuit consists of a first and a second transistor and said second polarity inverting circuit consists of a third and a fourth transistors, each said first, second, third and fourth transistors having an input terminal and first and second output terminals and said first output terminal of each of said first and third transistors being commonly connected with one end of said first power source means, said second output terminals of said first and third transistors being connected respectively with said first output terminals of said second and fourth transistors, said second output terminals of said second and fourth transistors being connected with the other end of said first power source means; each unit circuit further including a fifth transistor having an input terminal connected with said second power source means, a first output terminal connected with one of said first output terminals of said second and fourth transistors and a second output terminal connected with one of said input terminals of said fourth transistor and said output means.

Claim 7

A scanning circuit as claimed in claim 3, wherein said first and second output terminals of said fifth transistor are connected with said first output terminal of said fourth transistor and said output means, respectively.

Claim 8

A scanning circuit comprising: a circuit means consisting of a plurality of cascade-connected circuits, each unit circuit having a first and a second polarity inverting circuit and the output of said first polarity inverting circuit being fed as an input to said second polarity inverting circuit; a first power source means to supply DC power for each of said unit circuits; an input means to apply an input signal to the first stage of said circuit means; and an output means to take out the output of said second polarity inverting circuit of each of said unit circuits, wherein said first polarity inverting circuit includes a first and a second MOS transistor, each transistor having an input terminal and first and second output terminals, and said second polarity inverting circuit includes a third and a fourth MOS transistor, each transistor having an input terminal and first and second output terminals, said input terminal and said first output terminal of each of said first and third transistors being commonly connected with one terminal of said first power source means, said second output terminals of said first and third transistors being connected with said first output terminals of said second and fourth transistors, respectively, said second output terminals of said second and fourth transistors being connected with the other terminals of said first power source means, said first output terminal of said second transistor being connected with said input terminal of said fourth transistor, said first output terminal of said fourth transistor being connected with said output means; further comprising a second power source means and a fifth MOS transistor provided in each unit circuit of said circuit means, said fifth transistor having an input terminal and a first and a second output terminals, said input terminal of said fifth transistor being connected with said second power source means, and said first and second output terminals of said fifth transistor being connected respectively with said first output terminal of said second transistor and said input terminal of said fourth transistor; further comprising in each unit circuit of said circuit means a sixth MOS transistor having an input terminal and a first and a second output terminals, said input terminal of said sixth transistor being connected with said second power source means and said first and second output terminals of said sixth transistor being connected respectively with said first output terminal of said fourth transistor and said output means; wherein said second power source comprises a DC power source.

Claim 9

A scanning circuit comprising: a circuit means consisting of a plurality of cascade-connected circuits, each unit circuit having a first and a second polarity inverting circuit and the output of said first polarity inverting circuit being fed as an input to said second polarity inverting circuit; a first power source means to supply DC power for each of said unit circuits; an input means to apply an input signal to the first stage of said circuit means; and an output means to take out the output of said second polarity inverting circuit of each of said unit circuits, wherein said first polarity inverting circuit includes a first and a second MOS transistor, each transistor having an input terminal and first and second output terminals, and said second polarity inverting circuit includes a third and a fourth MOS transistor, each transistor having an input terminal and first and second output terminals, said input terminal and said first output terminal of each of said first and third transistors being commonly connected with one terminal of said first power source means, said second output terminals of said first and third transistors being connected with said first output terminals of said second and fourth transistors, respectively, said second output terminals of said second and fourth transistors being connected with the other terminals of said first power source means, said first output terminal of said second transistor being connected with said input terminal of said fourth transistor, said first output terminal of said fourth transistor being connected with said output means; further comprising a second power source means and a fifth MOS transistor provided in each unit circuit of said circuit means, said fifth transistor having an input terminal and a first and a second output terminals, said input terminal of said fifth transistor being connected with said second power source means, and said first and second output terminals of said fifth transistor being connected respectively with said first output terminal of said second transistor and said input terminal of said fourth transistor; further comprising in each unit circuit of said circuit means a sixth MOS transistor having an input terminal and a first and a second output terminals, said input terminal of said sixth transistor being connected with said second power source means and said first and second output terminals of said sixth transistor being connected respectively with said first output terminal of said fourth transistor and said output means; wherein said second power source comprises a DC power source.