Active delay line

Claim 2

A delay line according to claim 1 wherein said output circuit means are AND circuits.

Claim 3

A delay line according to claim 3 wherein each of said AND circuits includes an input for selectively inhibiting output pulses therefrom.

Claim 4

A delay line comprising: a series of active time delay inverting circuits interconnected each to delay the leading edge of a pulse applied thereto by a predetermined period of time required to change said circuit from one state of conduction to another, and each to invert the pulse applied thereto so that said series line provides inverted and noninverted pulses in alternating succession; circuit means for applying an input pulse to said time delay inverting circuits for propagation down said series line; and a plurality of AND circuits each being connected to said inverting circuits to receive an inverted pulse and a noninverted pulse, and each being operative to produce time delayed output pulses delayed in time from the input pulse and having a duration controlled by the leading edge of the input pulse being propagated down said series line.

Claim 5

A delay line according to claim 5 wherein each of said time delay inverting circuits is an amplifier circuit operating in a switching mode between conducting and nonconducting states.

Claim 6

A delay line according to claim 6 wherein said amplifiers are integrated circuits each having substantially the same turn-on time delay.

Claim 7

A delay line according to claim 5 wherein an odd number of said active circuits is connected between the inputs to each of said AND circuits.

Claim 8

A delay line according to claim 8 wherein said odd number is three.

Claim 9

A delay line according to claim 7, wherein at least two of said amplifiers are included in a single integrated circuit unit.

Claim 10

A delay line comprising a plurality of semiconductive means having inputs and outputs connected in series circuit and each having associated therewith a time delay between different conducting states to respond seriatim to an input signal applied to the input of the first thereof; and at least one AND circuit responsive to the leading edges of the signals at one of said inputs and one of said outputs to produce a time-delayed output signal having a duration related to the time separation of said leading edges.

Claim 11

A delay line as set forth in claim 11, wherein the semiconductive means comprises a transistor amplifier operative to provide an inverted output.

Claim 12

A delay line as specified in claim 12, whereiN each transistor amplifier operates in a switching mode between opposite states of conduction.

Claim 13

A delay line in accordance with claim 12, wherein said transistor amplifiers are direct coupled.