Decoders and coupling circuits for solid state video pickup

Claim 2

In combination: a first circuit point; a circuit node; a second circuit point; transducing means connected between said second circuit point and said circuit node for supplying an output current to said node in response to an excitation signal; charge storage means connected between said circuit node and said first circuit point for accumulating a charge in response to said output current produced by said transducer means; signal voltage responsive means connected at its input terminal to said circuit node and having also an output terminal, for producing at said output terminal a signal of an amplitude proportional to the amount of accumulated charge; sampling means directly connected to said first circuit point for normally placing the voltage at said first circuit point at a level sufficient to prevent conduction of said signal voltage responsive means in response to the maximum charge normally accumulated in said storage means and for subsequently placing the voltage level of said first circuit point at a level having a value sufficient to enable conduction through said voltage responsive means of the charge stored in said storage means; and means in said signal voltage responsive means for discharging said charge storage means when said voltage responsive means is enabled.

Claim 3

The combination as claimed in claim 1 wherein said voltage responsive means includes a diode having its anode connected to said charge storage means at said circuit node and its cathode connected to said output terminal, and including impedance means connecting said output terminal to a point of reference potential; and wherein said sampling means switches the potential at said circuit node from a high value of potential to a low value of potential for establishing a negative potential at the anode of said diode with respect to the potential at said point of reference potential whereby said diode is rendered non-conducting and then switches the potential from said low value of potential to said high value of potential in a direction to forward bias said diode and cause current to flow from said chaRge storage means to said output terminal.

Claim 4

The combination as claimed in claim 2 further including a second diode having its anode connected to the anode of said diode and its cathode connected to a second output terminal and further including biasing means applied at the cathode of said second diode for blocking signals of less than a given value from flowing through said second diode.

Claim 5

In the combination as claimed in claim 2 wherein the switching of said sampling pulses cause switching transient signals to be coupled through said diode and be mixed with the sensing element signal further including: a second diode having its anode connected to the anode of said diode and its cathode connected to a second output terminal; and reverse biasing means applied at the cathode of said second diode of sufficient amplitude to block the passage of said sensing element signal but permit the passage of switching transient signals whereby the signals at said first and second output terminals may be subtracted to produce a virtually transient free output signal.

Claim 6

The combination as claimed in claim 1 wherein said voltage responsive means includes a transistor having its base connected to said charge storage means at said circuit node and its emitter connected to said output terminal and further including first impedance means connecting said output terminal to a point of reference potential and second impedance means connecting the collector of said transistor to a source of operating potential; and wherein said sampling means switches the potential at said other end of said charge storage means from a high value of potential to a low value of potential for establishing a negative potential at the base of said transistor with respect to the potential at its emitter whereby said transistor is rendered non-conductive, and then switches the potential from said low value to said high value to forward bias the base with respect to the emitter and cause signal current to flow into the base-to-emitter path and an amplified current to flow through the collector-to-emitter path of said transistor into said output terminal.

Claim 7

The combination as claimed in claim 1 wherein said sampling means is coupled between said first circuit point and a point of reference potential thereby providing a return path for said charge storing means; and wherein said signal responsive means includes impedance means connected between said output terminal and said point of reference potential.

Claim 8

In combination: a sensing element for producing a current in response to an excitation signal; a transistor having base, emitter and collector; a charge storage means connected at one terminal both to the base of said transistor and to said sensor for accumulating charge and developing a signal potential in response to the excitation of said sensor; two valued pulse generating sampling means coupled between the other terminal of said charge storage means and the emitter of said transistor for reverse biasing the emitter of said transistor with respect to its base when said pulse is at one of its two level conditions and for applying a forward bias to the emitter with respect to the base when said pulse is at its other level condition, said transistor of the type which when reverse biased has a very high input impedance whereby no current flows through it and the current from said sensing element charges said charge storage means and when forward biased has a low impedance whereby it conducts the charge on said charge storage means across its base-to-emitter path for producing an amplified current in its collector-to-emitter path and concurrently discharging said charge storage means.

Claim 9

In combination: a sensing element for producing a current in response to an excitation signal; a transistor having base, emitter and collector; a charge storage means connected at one terminal both to the base of said transistor and to said sensor for accumulating charge and developing a signal potential in response to the excitation of said sensor; two valued pulse generating sampling means coupled between the other terminal of said charge storage means and the emitter of said transistor for reverse biasing the emitter of said transistor with respect to its base when said pulse is at one of its two level conditions and for applying a forward bias to the emitter with respect to the base when said pulse is at its other level condition, said transistor of the type which when reverse biased has a very high input impedance whereby no current flows through it and the current from said sensing element charges said charge storage means and when forward biased has a low impedance whereby it conducts the charge on said charge storage means across its base-to-emitter path for producing an amplified current in its collector-to-emitter path and concurrently discharging said charge storage means.

Claim 10

The combination as claimed in claim 7 wherein said other terminal of said charge storage means is returned to a point of fixed reference potential and wherein said sampling means provides a return path between the emitter of said transistor and said point of fixEd reference potential.

Claim 11

A matrix array of transducing elements arranged in rows and columns wherein an element is connected between each row and each column; first scanning means directly connected to one of said rows and columns for sequentially sampling said one of said rows and columns; a plurality of transistors each transistor having its base connected to a different one of the other one of said rows and columns and its collector connected in common with the collectors of the other transistors to an output terminal; charge storage means associated with the other one of said rows and columns and connected at one end to a different one of said transistors; second scanning means coupled between the other end of said charge storage means and the emitters of said plurality of transistors for sequentially sampling the emitters of said transistors, said second scanning means producing pulses having a first value for reverse biasing the base-to-emitter region of said transistors, whereby said transistors are rendered non-conductive and said charge storage means accumulate the charge produced by the elements connected to their associated columns and producing pulses having a second value for forward biasing the emitter-to-base region of said transistors for causing the charge stored in said charge storage means to be discharged through the base-to-emitter region of said transistor and for concurrently causing a corresponding amplified current to flow in the collector-to-emitter path of the transistor.

Claim 12

A matrix array of transducing elements arranged in rows and columns wherein an element is connected between each row and each column; first scanning means directly connected to one of said rows and columns for sequentially sampling said one of said rows and columns; a plurality of transistors each transistor having its base connected to a different one of the other one of said rows and columns and its collector connected in common with the collectors of the other transistors to an output terminal; charge storage means associated with the other one of said rows and columns and connected at one end to a different one of said transistors; second scanning means coupled between the other end of said charge storage means and the emitters of said plurality of transistors for sequentially sampling the emitters of said transistors, said second scanning means producing pulses having a first value for reverse biasing the base-to-emitter region of said transistors, whereby said transistors are rendered non-conductive and said charge storage means accumulate the charge produced by the elements connected to their associated columns and producing pulses having a second value for forward biasing the emitter-to-base region of said transistors for causing the charge stored in said charge storage means to be discharged through the base-to-emitter region of said transistor and for concurrently causing a corresponding amplified current to flow in the collector-to-emitter path of the transistor.

Claim 13

In combination with a matrix array of elements connected between two sets of intersecting conductors, a coupling circuit comprising: a plurality of charge storage means, and a plurality of signal coupling means; means coupling each one of said signal coupling means between one end of a different one of said charge storage means and an output terminal; impedance means coupling said output terminal to a point of reference potential; means coupling said one end of said charge storage means to a different one of the conductors of one set of said two sets of conductors; and sequencing means coupled between the other end of said charge storage means and said point of reference potential for sequentially sampling the contents of said storage means; said sequencing means applying pulses to said charge storage means for coupling therethrough negative and positive going voltage steps for under one condition rendering said signal coupling means non-conducting and causing the signal produced by the elements of said array to accumulate charge on their respective charge storage means and for under the other condition rendering said signal coupling means conducting for producing an output signal at said output terminal proportional to the stored charge and for concurrently discharging the charge storage means associated with the selected signal coupling means.

Claim 14

In combination with a matrix array of elements connected between two sets of intersecting conductors, a coupling circuit comprising: a plurality of charge storage means, and a plurality of signal coupling means; means coupling each one of said signal coupling means between one end of a different one of said charge storage means and an output terminal; impedance means coupling said output terminal to a point of reference potential; means coupling said one end of said charge storage means to a different one of the conductors of one set of said two sets of conductors; and sequencing means coupled between the other end of said charge storage means and said point of reference potential for sequentially sampling the contents of said storage means; said sequencing means applying pulses to said charge storage means for coupling therethrough negative and positive going voltage steps for under one condition rendering said signal coupling means non-conducting and causing the signal produced by the elements of said array to accumulate charge on their respective charge storage means and for under the other condition rendering said signal coupling means conducting for producing an output signal at said output terminal proportional to the stored charge and for concurrently discharging the charge storage means associated with the selected signal coupling means.

Claim 15

In combination: transducer means for producing signal current in response to an excitation signal; two parallel current paths connected between said transducer means and a point of reference potential, one of said paths comprising charge storage means and the other one of said paths including the base-to-emitter diode of a bipolar transistor poled to conduct the current from said transducer means in the forward direction; sampling means connected between the emitter of said transistor and said storage means; means responsive to a sampling signal transition from a first level to a second level for maintaining said base-to-emitter diode cut off and thereby causing said signal current, when present, to charge said charge storage means and responsive to a sampling signal transition from said second level to said first level for placing said base-to-emitter diode in a conducting condition, whereby said charge storage means, if charged to greater than a given value, discharges into said transistor; and an output circuit coupled to the collector of said bipolar traNsistor and responsive to current flow in the base-to-emitter diode, for producing an amplified output signal.

Claim 16

In combination: transducer means for producing signal current in response to an excitation signal; two parallel current paths connected between said transducer means and a point of reference potential, one of said paths comprising charge storage means and the other one of said paths including the base-to-emitter diode of a bipolar transistor poled to conduct the current from said transducer means in the forward direction; sampling means connected between the emitter of said transistor and said storage means; means responsive to a sampling signal transition from a first level to a second level for maintaining said base-to-emitter diode cut off and thereby causing said signal current, when present, to charge said charge storage means and responsive to a sampling signal transition from said second level to said first level for placing said base-to-emitter diode in a conducting condition, whereby said charge storage means, if charged to greater than a given value, discharges into said transistor; and an output circuit coupled to the collector of said bipolar traNsistor and responsive to current flow in the base-to-emitter diode, for producing an amplified output signal.

Claim 17

The combination as claimed in claim 11 further providing load means connected to the emitter and collector of said bipolar transistor for producing two output signals thereat one being out-of-phase with respect to the other.

Claim 18

The combination as claimed in claim 12 wherein said charge storage means is a capacitor.

Claim 19

The combination as claimed in claim 12 wherein said sampling means is coupled in series with said charge storage means between said transducer means and said point of reference potential.