EP0171720B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data delay/memory circuit
Assignee: Toshiba Corp
•
Filing: 1985-08-02
•
Granted: 1991-05-29
•
Expires: 2005-08-02
Abstract
No abstract record available.
Inventors
- 👤 Sigeru C/O Patent Division Nose
- 👤 Seigo C/O Patent Division Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 20:18
CPC Classifications
G; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
89 words
A data delay/memory circuit comprising: - a data shift circuit formed of a plurality of at least three clock-controlled data latch circuits (I1-I7) which are cascade-connected; characterized by - means (CG) for supplying said plurality of at least three data latch circuits (I1-I7) with clock signals (φ1-φ7) having individual clocking phases and being sequentially generated such that the clocking phase (φ1) for a final stage (I7) of said data latch circuits (I1-I7) is ahead of that (φ7) for an initial stage (I1) of said data latch circuits (Fig. 1).
Claim 2
Dependent Claim
22 words
A data delay/memory circuit according to claim 1, characterized in that each of said data latch circuits is of a dynamic type.
Claim 3
Dependent Claim
19 words
A data delay/memory circuit according to claim 2, characterized in that said dynamic data latch circuits include clocked inverters.
Claim 4
Dependent Claim
41 words
A data delay/memory circuit according to claim 1 , characterized in that said supplying means (CG) is provided with wirings (W10-W23) for feeding said clock signals (φ1-φ7) which geometrically cross the data transfer direction of said cascade-connected plural data latch circuits.
Claim 5
Dependent Claim
114 words
A data delay/memory circuit according to claim 1, characterized by comprising: - a plurality of data delay/memory circuits (DMC1-DMC6) each being formed of said plurality of at least three clock-controlled and cascade-connected data latch circuits (I1A-I7F); - serial/parallel converter means (SPC), coupled to said data delay/memory circuits (DMC1-DMC6) and responsive to serial input data (DX), for supplying respective input terminals of said data latch circuits (I1A-I1F) with data (Din1-Din6) having individual phases with respect to said serial input data (DX); and - parallel/serial converter means (PSC), coupled to said data delay/memory circuits (DMC1-DMC6), for converting data (Dout1-Dout6) delivered from the respective output terminals of said data latch circuits (I1A-I1F) into serial output data (DY).
Claim 6
Dependent Claim
43 words
A data delay/memory circuit according to claim 5, characterized in that each of said serial/parallel converter means (SPC) and said parallel/serial converter means (PSC) is controlled by a master clock signal and formed of a plurality of cascade-connected data delay circuits (DL10-DL20, DL22-DL32).
Claim 7
Dependent Claim
46 words
A data delay/memory circuit according to claim 5, characterized in that each delay time of the respective signals in said plural data delay/memory circuits (DMC1-DMC6), which are associated with said serial/parallel converter means (SPC) and said parallel/serial converter means (PSC), is set at a prescribed value.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.